SikongJueluo ca167e79c6 refactor(hw/sim): extract common cocotb make infrastructure into shared mk/ directory ...

- Split monolithic hw/sim/Makefile into modular include files (mk/cocotb-common.mk, mk/rtl-sources.mk)
- Add per-module test Makefiles (cam_core_banked, cam_read_noise, cam_write_noise, match_engine_pipeline, perf, top)
- Add missing simulation tools (yosys, graphviz, xdot) to devenv.nix
- Fix path handling in sweep_noise.py and test modules to be HASH_BITS-aware

2026-05-16 19:24:17 +08:00

.opencode

chore(project): adjust safety rules

2026-05-15 14:03:40 +08:00

docs

refactor: reorganize RTL files into core/noise subdirectories

2026-05-14 20:59:46 +08:00

hw

refactor(hw/sim): extract common cocotb make infrastructure into shared mk/ directory

2026-05-16 19:24:17 +08:00

mini-nav

refactor(benchmark): delegate model loading to tasks and support CIFAR-100

2026-05-15 09:59:40 +08:00

notebooks

refactor(visualization): enhance proposal filtering visualization

2026-04-18 23:24:30 +08:00

scripts

feat(sim): add CAM performance sweep test infrastructure

2026-05-16 15:42:29 +08:00

tests

feat(sim): add CAM performance sweep test infrastructure

2026-05-16 15:42:29 +08:00

.editorconfig

build(simulation): improve verilator simulation infrastructure

2026-05-03 15:33:17 +08:00

.envrc

chore(project): update .envrc and justfile for server, and update marimo

2026-04-18 21:10:22 +08:00

.gitignore

chore(project): adjust safety rules

2026-05-15 14:03:40 +08:00

.justfile

feat(dev): add CAM test recipes and update ignore files

2026-05-13 18:22:14 +08:00

.python-version

chore: use micromamba and uv to manage python environment

2026-03-18 20:14:30 +08:00

.safety-net.json

chore(project): adjust safety rules

2026-05-15 14:03:40 +08:00

.stignore

feat(dev): add CAM test recipes and update ignore files

2026-05-13 18:22:14 +08:00

AGENTS.md

chore: migrate habitat dependencies to conda and add cocotb for hardware verification

2026-05-02 23:24:59 +08:00

CLAUDE.md

chore: migrate habitat dependencies to conda and add cocotb for hardware verification

2026-05-02 23:24:59 +08:00

devenv.lock

refactor: reorganize RTL files into core/noise subdirectories

2026-05-14 20:59:46 +08:00

devenv.nix

refactor(hw/sim): extract common cocotb make infrastructure into shared mk/ directory

2026-05-16 19:24:17 +08:00

devenv.yaml

feat(feature-compressor): add DINOv2 feature extraction and compression pipeline

2026-01-31 10:34:22 +08:00

environment.yml

build(simulation): improve verilator simulation infrastructure

2026-05-03 15:33:17 +08:00

LICENSE

Initial commit

2026-01-19 15:24:36 +08:00

pyproject.toml

chore(project): adjust safety rules

2026-05-15 14:03:40 +08:00

uv.lock

refactor(benchmark): delegate model loading to tasks and support CIFAR-100

2026-05-15 09:59:40 +08:00

Description

No description provided

MIT 3 MiB

Languages

Python 88.8%

SystemVerilog 8.9%

Makefile 2.2%

Nix 0.1%