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- Split monolithic hw/sim/Makefile into modular include files (mk/cocotb-common.mk, mk/rtl-sources.mk) - Add per-module test Makefiles (cam_core_banked, cam_read_noise, cam_write_noise, match_engine_pipeline, perf, top) - Add missing simulation tools (yosys, graphviz, xdot) to devenv.nix - Fix path handling in sweep_noise.py and test modules to be HASH_BITS-aware
10 lines
253 B
Makefile
10 lines
253 B
Makefile
SIM_ROOT := $(abspath ../..)
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RTL_ROOT := $(abspath $(SIM_ROOT)/../rtl)
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include $(SIM_ROOT)/mk/rtl-sources.mk
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TOPLEVEL := cam_top
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COCOTB_TEST_MODULES := tests.top.test_cam_basic
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VERILOG_SOURCES := $(RTL_CAM_TOP)
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include $(SIM_ROOT)/mk/cocotb-common.mk
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