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SikongJueluo
0dd01fb1b7
- Add random32, random64 and random128 xorshift PRNG modules - Refactor cam_noisy FSM: split state register, next-state logic, and datapath into distinct blocks - Rename state_q/state_d to curr_state/next_state for clarity - Add MASK_GROUPS localparam and fix type casting in noise generation - Update .gitignore to exclude docs/superpowers
29 lines
608 B
Systemverilog
29 lines
608 B
Systemverilog
`timescale 1ns / 1ps
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module random64 (
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input logic clk,
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input logic rst_n,
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input logic enable,
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input logic [63:0] seed,
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output logic [63:0] out
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);
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function automatic logic [63:0] xorshift64(input logic [63:0] x);
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logic [63:0] s;
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s = x;
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s ^= s << 13;
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s ^= s >> 7;
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s ^= s << 17;
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return s;
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endfunction
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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out <= seed;
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end else if (enable) begin
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out <= xorshift64(out);
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end
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end
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endmodule
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