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https://github.com/SikongJueluo/Mini-Nav.git
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SikongJueluo
8b4d4c1b57
- Make cam_read_noise a pass-through module, removing all noise injection logic - Switch write noise to use noise_mask_bernoulli instead of noise_mask_grouped - Add state machine to cam_write_noise for mask generation timing - Remove noise_mask_grouped.sv (no longer needed) - Remove read noise parameters from cam_noisy and cam_top - Update simulation and benchmark code to reflect read noise removal - Sync documentation to reflect Phase 2 architecture
83 lines
3.0 KiB
Systemverilog
83 lines
3.0 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "cam_params.svh"
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module cam_noisy #(
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parameter bit WRITE_NOISE_EN = 1'b1,
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parameter int WRITE_NOISE_RATE_NUM = 1,
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parameter int WRITE_NOISE_RATE_DEN = 100,
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parameter logic [63:0] WRITE_NOISE_SEED = 64'hB504_F32D_B504_F32D
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) (
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input logic clk,
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input logic rst_n,
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input logic wr_valid,
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output logic wr_ready,
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input logic [(`ROW_BITS)-1:0] wr_addr,
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input logic [(`HASH_BITS)-1:0] write_hash,
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input logic rd_valid_i,
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input logic [(`ROW_BITS)-1:0] rd_base_row_i,
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output logic rd_valid_o,
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output logic [(`LANES)*(`ROW_BITS)-1:0] rd_row_ids_o,
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output logic [(`LANES)*(`HASH_BITS)-1:0] rd_hashes_o,
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output logic [(`LANES)-1:0] rd_lane_valid_o
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);
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// ── Intermediate wires between pipeline stages ──
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logic core_wr_valid;
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logic [(`ROW_BITS)-1:0] core_wr_row;
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logic [(`HASH_BITS)-1:0] core_wr_hash;
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logic core_rd_valid;
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logic [(`LANES)*(`ROW_BITS)-1:0] core_rd_row_ids;
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logic [(`LANES)*(`HASH_BITS)-1:0] core_rd_hashes;
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logic [(`LANES)-1:0] core_rd_lane_valid;
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// ── Write noise pipeline ──
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cam_write_noise #(
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.WRITE_NOISE_EN (WRITE_NOISE_EN),
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.WRITE_NOISE_RATE_NUM (WRITE_NOISE_RATE_NUM),
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.WRITE_NOISE_RATE_DEN (WRITE_NOISE_RATE_DEN),
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.WRITE_NOISE_SEED (WRITE_NOISE_SEED)
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) u_write_noise (
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.clk (clk),
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.rst_n (rst_n),
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.wr_valid (wr_valid),
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.wr_ready (wr_ready),
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.wr_row (wr_addr),
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.wr_hash (write_hash),
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.core_wr_valid (core_wr_valid),
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.core_wr_row (core_wr_row),
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.core_wr_hash (core_wr_hash)
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);
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// ── Banked synchronous BRAM storage ──
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cam_core_banked u_core_banked (
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.clk (clk),
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.rst_n (rst_n),
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.wr_valid (core_wr_valid),
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.wr_ready (),
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.wr_row (core_wr_row),
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.wr_hash (core_wr_hash),
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.rd_valid_i (rd_valid_i),
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.rd_base_row_i (rd_base_row_i),
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.rd_valid_o (core_rd_valid),
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.rd_row_ids_o (core_rd_row_ids),
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.rd_hashes_o (core_rd_hashes),
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.rd_lane_valid_o (core_rd_lane_valid)
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);
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// ── Read noise pipeline ──
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cam_read_noise u_read_noise (
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.clk (clk),
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.rst_n (rst_n),
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.valid_i (core_rd_valid),
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.row_ids_i (core_rd_row_ids),
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.hashes_i (core_rd_hashes),
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.lane_valid_i (core_rd_lane_valid),
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.valid_o (rd_valid_o),
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.row_ids_o (rd_row_ids_o),
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.hashes_noisy_o (rd_hashes_o),
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.lane_valid_o (rd_lane_valid_o)
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);
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endmodule
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