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https://github.com/SikongJueluo/Mini-Nav.git
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SikongJueluo
8f59a287c4
- Add cam_core_banked.sv with 8-lane banked CAM core - Add cam_write_noise.sv and cam_read_noise.sv for grouped noise injection - Add noise_mask_grouped.sv generating grouped flip masks from 128-bit PRNG - Add match_engine_pipeline.sv with multi-stage pipelined top-1 selection - Add popcount_pipeline.sv for pipelined popcount operations - Refactor test_cam_basic.py with parametrized DUT introspection helpers - Add Python ref_model match_top1_with_read_noise() for read noise verification - Update Makefile with separate WRITE_NOISE_* and READ_NOISE_* parameter groups - Add new testbenches: test_cam_core_banked, test_cam_read_noise, test_cam_write_noise, test_match_engine_pipeline, test_ref_model_noise breaking change hint: NUM_ROWS default changed from 512→4096, LANES from 16→8
76 lines
2.4 KiB
Systemverilog
76 lines
2.4 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "cam_params.svh"
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module cam_write_noise #(
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parameter bit WRITE_NOISE_EN = 1'b1,
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parameter int WRITE_NOISE_RATE_NUM = 1,
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parameter int WRITE_NOISE_RATE_DEN = 100,
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parameter int WRITE_NOISE_BITS = 8,
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parameter logic [63:0] WRITE_NOISE_SEED = 64'hB504_F32D_B504_F32D
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) (
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input logic clk,
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input logic rst_n,
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input logic wr_valid,
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output logic wr_ready,
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input logic [(`ROW_BITS)-1:0] wr_row,
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input logic [(`HASH_BITS)-1:0] wr_hash,
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output logic core_wr_valid,
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output logic [(`ROW_BITS)-1:0] core_wr_row,
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output logic [(`HASH_BITS)-1:0] core_wr_hash
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);
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logic pending_q;
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logic [(`ROW_BITS)-1:0] row_q;
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logic [(`HASH_BITS)-1:0] hash_q;
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logic [127:0] random_num;
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logic [(`HASH_BITS)-1:0] flip_mask;
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assign wr_ready = !pending_q;
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random128 u_random_write (
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.clk (clk),
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.rst_n (rst_n),
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.enable(wr_valid && wr_ready && WRITE_NOISE_EN && (WRITE_NOISE_RATE_NUM > 0)),
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.seed ({WRITE_NOISE_SEED, WRITE_NOISE_SEED}),
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.out (random_num)
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);
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noise_mask_grouped #(
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.HASH_BITS (`HASH_BITS),
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.NOISE_BITS (WRITE_NOISE_BITS),
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.NOISE_RATE_NUM (WRITE_NOISE_RATE_NUM),
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.NOISE_RATE_DEN (WRITE_NOISE_RATE_DEN)
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) u_mask (
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.random_i(random_num),
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.mask_o (flip_mask)
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);
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initial begin
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if (WRITE_NOISE_SEED == 64'd0) $fatal(1, "WRITE_NOISE_SEED must be nonzero");
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end
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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pending_q <= 1'b0;
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row_q <= '0;
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hash_q <= '0;
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core_wr_valid <= 1'b0;
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core_wr_row <= '0;
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core_wr_hash <= '0;
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end else begin
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core_wr_valid <= pending_q;
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core_wr_row <= row_q;
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if (WRITE_NOISE_EN && (WRITE_NOISE_RATE_NUM > 0)) begin
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core_wr_hash <= hash_q ^ flip_mask;
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end else begin
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core_wr_hash <= hash_q;
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end
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pending_q <= wr_valid && wr_ready;
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if (wr_valid && wr_ready) begin
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row_q <= wr_row;
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hash_q <= wr_hash;
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end
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end
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end
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endmodule
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