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SikongJueluo
8b4d4c1b57
- Make cam_read_noise a pass-through module, removing all noise injection logic - Switch write noise to use noise_mask_bernoulli instead of noise_mask_grouped - Add state machine to cam_write_noise for mask generation timing - Remove noise_mask_grouped.sv (no longer needed) - Remove read noise parameters from cam_noisy and cam_top - Update simulation and benchmark code to reflect read noise removal - Sync documentation to reflect Phase 2 architecture
32 lines
1.0 KiB
Systemverilog
32 lines
1.0 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "cam_params.svh"
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module cam_read_noise (
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input logic clk,
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input logic rst_n,
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input logic valid_i,
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input logic [(`LANES)*(`ROW_BITS)-1:0] row_ids_i,
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input logic [(`LANES)*(`HASH_BITS)-1:0] hashes_i,
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input logic [(`LANES)-1:0] lane_valid_i,
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output logic valid_o,
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output logic [(`LANES)*(`ROW_BITS)-1:0] row_ids_o,
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output logic [(`LANES)*(`HASH_BITS)-1:0] hashes_noisy_o,
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output logic [(`LANES)-1:0] lane_valid_o
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);
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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valid_o <= 1'b0;
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row_ids_o <= '0;
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hashes_noisy_o <= '0;
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lane_valid_o <= '0;
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end else begin
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valid_o <= valid_i;
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row_ids_o <= row_ids_i;
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hashes_noisy_o <= hashes_i;
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lane_valid_o <= lane_valid_i;
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end
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end
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endmodule
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