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715a2c2ed695cc8fcd0e16fac57fcb82758ae741
- Add docs/architecture/cam_hardware_block_design.drawio - Diagram illustrates CAM top-level architecture including: - Host write path with write-priority half-duplex arbiter - Write noise injector with Bernoulli flip mask - Banked CAM storage (8 BRAM banks × 512 depth) - 8-lane match engine pipeline with popcount - Top-K tracker and result serializer - Supports documentation for 4096-row × 512-bit hash CAM design
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