mirror of
https://github.com/SikongJueluo/Mini-Nav.git
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SikongJueluo
706d148a0b
- Add hw/syn/Makefile with hier/flat/full synth targets and artifact mirroring - Add synth_cam_top_hier.ys for hierarchy-preserving resource estimation on Xilinx 7-series - Add synth_cam_top_flat.ys for flattened Xilinx 7-series synthesis - Add cam-synth just target for convenient invocation - Guard runtime assertions (NUM_ROWS/LANES checks, noise seed checks, NOISE_BITS checks) behind SYNTHESIS guard in cam_core_banked, cam_read_noise, cam_write_noise, and noise_mask_grouped - Fix shadowed 'return' variable in random128 xorshift128 function
41 lines
1.3 KiB
Plaintext
41 lines
1.3 KiB
Plaintext
# synth_cam_top_hier.ys — Hierarchy-preserving CAM top resource reference flow
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# Run from hw/syn: yosys -s synth_cam_top_hier.ys
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# Set include directories before reading RTL
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verilog_defaults -push
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verilog_defaults -add -I../rtl
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verilog_defaults -add -I../rtl/core
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verilog_defaults -add -I../rtl/noise
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verilog_defaults -add -I../rtl/random
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# Read RTL sources in canonical order
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read_verilog -sv -D SYNTHESIS ../rtl/random/random128.sv
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read_verilog -sv -D SYNTHESIS ../rtl/noise/noise_mask_grouped.sv
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read_verilog -sv -D SYNTHESIS ../rtl/noise/cam_write_noise.sv
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read_verilog -sv -D SYNTHESIS ../rtl/noise/cam_read_noise.sv
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read_verilog -sv -D SYNTHESIS ../rtl/core/cam_core_banked.sv
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read_verilog -sv -D SYNTHESIS ../rtl/core/popcount_pipeline.sv
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read_verilog -sv -D SYNTHESIS ../rtl/core/match_engine_pipeline.sv
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read_verilog -sv -D SYNTHESIS ../rtl/cam_noisy.sv
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read_verilog -sv -D SYNTHESIS ../rtl/cam_top.sv
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# Restore verilog defaults
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verilog_defaults -pop
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# Hierarchy check and elaboration
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hierarchy -top cam_top -check
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# Process and optimize
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proc
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opt
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memory -nomap
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# Ensure build directory exists for output files
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exec -- mkdir -p build
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# Resource statistics (JSON to file via tee, not mixed into logs)
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tee -q -o build/cam_top_hier_resources.json stat -tech xilinx -json
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# Final checks
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check -noinit
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