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https://github.com/SikongJueluo/Mini-Nav.git
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SikongJueluo
706d148a0b
- Add hw/syn/Makefile with hier/flat/full synth targets and artifact mirroring - Add synth_cam_top_hier.ys for hierarchy-preserving resource estimation on Xilinx 7-series - Add synth_cam_top_flat.ys for flattened Xilinx 7-series synthesis - Add cam-synth just target for convenient invocation - Guard runtime assertions (NUM_ROWS/LANES checks, noise seed checks, NOISE_BITS checks) behind SYNTHESIS guard in cam_core_banked, cam_read_noise, cam_write_noise, and noise_mask_grouped - Fix shadowed 'return' variable in random128 xorshift128 function
40 lines
1.6 KiB
Systemverilog
40 lines
1.6 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "cam_params.svh"
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module noise_mask_grouped #(
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parameter int HASH_BITS = `HASH_BITS,
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parameter int NOISE_BITS = 8,
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parameter int NOISE_RATE_NUM = 1,
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parameter int NOISE_RATE_DEN = 100
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) (
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input logic [127:0] random_i,
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output logic [HASH_BITS-1:0] mask_o
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);
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localparam int GROUP_BITS = HASH_BITS / NOISE_BITS;
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localparam int BIT_INDEX_BITS = 6;
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localparam int SAMPLE_BITS = 8;
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localparam int GROUP_RAND_BITS = BIT_INDEX_BITS + SAMPLE_BITS;
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localparam int SAMPLE_RANGE = 1 << SAMPLE_BITS;
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localparam int THRESHOLD = (NOISE_RATE_NUM * SAMPLE_RANGE) / NOISE_RATE_DEN;
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`ifndef SYNTHESIS
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initial begin
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if (NOISE_BITS <= 0) $fatal(1, "NOISE_BITS must be > 0");
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if (HASH_BITS % NOISE_BITS != 0) $fatal(1, "HASH_BITS must be divisible by NOISE_BITS");
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if (GROUP_BITS != 64) $fatal(1, "GROUP_BITS must be 64 for 6-bit grouped noise");
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if (NOISE_BITS * GROUP_RAND_BITS > 128) $fatal(1, "NOISE_BITS consumes more than 128 random bits");
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if (NOISE_RATE_DEN <= 0) $fatal(1, "NOISE_RATE_DEN must be > 0");
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if (NOISE_RATE_NUM < 0 || NOISE_RATE_NUM > NOISE_RATE_DEN) $fatal(1, "NOISE_RATE_NUM out of range");
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end
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`endif
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always_comb begin
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mask_o = '0;
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for (int i = 0; i < NOISE_BITS; i++) begin
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if (random_i[i * GROUP_RAND_BITS + BIT_INDEX_BITS +: SAMPLE_BITS] < THRESHOLD) begin
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mask_o[i * GROUP_BITS + random_i[i * GROUP_RAND_BITS +: BIT_INDEX_BITS]] = 1'b1;
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end
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end
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end
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endmodule
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