SikongJueluo 706d148a0b feat(hw): add CAM top-level synthesis infrastructure and fix RTL synthesis compatibility ...

- Add hw/syn/Makefile with hier/flat/full synth targets and artifact mirroring
- Add synth_cam_top_hier.ys for hierarchy-preserving resource estimation on Xilinx 7-series
- Add synth_cam_top_flat.ys for flattened Xilinx 7-series synthesis
- Add cam-synth just target for convenient invocation
- Guard runtime assertions (NUM_ROWS/LANES checks, noise seed checks, NOISE_BITS checks)
  behind SYNTHESIS guard in cam_core_banked, cam_read_noise, cam_write_noise, and noise_mask_grouped
- Fix shadowed 'return' variable in random128 xorshift128 function

2026-05-18 15:40:04 +08:00

2.4 KiB

Raw Blame History

View Raw