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SikongJueluo
706d148a0b
- Add hw/syn/Makefile with hier/flat/full synth targets and artifact mirroring - Add synth_cam_top_hier.ys for hierarchy-preserving resource estimation on Xilinx 7-series - Add synth_cam_top_flat.ys for flattened Xilinx 7-series synthesis - Add cam-synth just target for convenient invocation - Guard runtime assertions (NUM_ROWS/LANES checks, noise seed checks, NOISE_BITS checks) behind SYNTHESIS guard in cam_core_banked, cam_read_noise, cam_write_noise, and noise_mask_grouped - Fix shadowed 'return' variable in random128 xorshift128 function
58 lines
1.3 KiB
Systemverilog
58 lines
1.3 KiB
Systemverilog
`timescale 1ns / 1ps
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module random128 (
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input logic clk,
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input logic rst_n,
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input logic enable,
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input logic [127:0] seed,
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output logic [127:0] out
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);
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// xorshift128:
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// state = {x, y, z, w}
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//
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// t = x ^ (x << 11)
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// x = y
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// y = z
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// z = w
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// w = w ^ (w >> 19) ^ t ^ (t >> 8)
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//
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// 注意：seed 不能为全 0，否则会永久输出 0。
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function automatic logic [127:0] xorshift128(input logic [127:0] state);
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logic [31:0] x;
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logic [31:0] y;
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logic [31:0] z;
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logic [31:0] w;
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logic [31:0] t;
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logic [31:0] next_x;
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logic [31:0] next_y;
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logic [31:0] next_z;
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logic [31:0] next_w;
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begin
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x = state[127:96];
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y = state[95:64];
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z = state[63:32];
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w = state[31:0];
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t = x ^ (x << 11);
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next_x = y;
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next_y = z;
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next_z = w;
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next_w = w ^ (w >> 19) ^ t ^ (t >> 8);
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xorshift128 = {next_x, next_y, next_z, next_w};
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end
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endfunction
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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out <= seed;
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end else if (enable) begin
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out <= xorshift128(out);
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end
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end
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endmodule
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