2 Commits

Author	SHA1	Message	Date
SikongJueluo	706d148a0b	feat(hw): add CAM top-level synthesis infrastructure and fix RTL synthesis compatibility ... - Add hw/syn/Makefile with hier/flat/full synth targets and artifact mirroring - Add synth_cam_top_hier.ys for hierarchy-preserving resource estimation on Xilinx 7-series - Add synth_cam_top_flat.ys for flattened Xilinx 7-series synthesis - Add cam-synth just target for convenient invocation - Guard runtime assertions (NUM_ROWS/LANES checks, noise seed checks, NOISE_BITS checks) behind SYNTHESIS guard in cam_core_banked, cam_read_noise, cam_write_noise, and noise_mask_grouped - Fix shadowed 'return' variable in random128 xorshift128 function	2026-05-18 15:40:04 +08:00
SikongJueluo	0dd01fb1b7	feat(hw/rtl): add xorshift PRNG modules and refactor cam_noisy FSM ... - Add random32, random64 and random128 xorshift PRNG modules - Refactor cam_noisy FSM: split state register, next-state logic, and datapath into distinct blocks - Rename state_q/state_d to curr_state/next_state for clarity - Add MASK_GROUPS localparam and fix type casting in noise generation - Update .gitignore to exclude docs/superpowers	2026-05-05 19:30:50 +08:00