3 Commits

Author	SHA1	Message	Date
SikongJueluo	8bcad1f23f	refactor(core/cam_core_banked): extract per-bank modules for improved timing isolation ... - Extract cam_bank as a parameterized submodule with independent read/write ports - Replace flat 2D memory array with generate loop of bank instances - Derive bank selection from address bit slicing instead of modulo arithmetic - Align rd_base_row_i check with new bank addressing scheme - Add test verifying bank address isolation across multiple banks	2026-05-19 16:17:08 +08:00
SikongJueluo	706d148a0b	feat(hw): add CAM top-level synthesis infrastructure and fix RTL synthesis compatibility ... - Add hw/syn/Makefile with hier/flat/full synth targets and artifact mirroring - Add synth_cam_top_hier.ys for hierarchy-preserving resource estimation on Xilinx 7-series - Add synth_cam_top_flat.ys for flattened Xilinx 7-series synthesis - Add cam-synth just target for convenient invocation - Guard runtime assertions (NUM_ROWS/LANES checks, noise seed checks, NOISE_BITS checks) behind SYNTHESIS guard in cam_core_banked, cam_read_noise, cam_write_noise, and noise_mask_grouped - Fix shadowed 'return' variable in random128 xorshift128 function	2026-05-18 15:40:04 +08:00
SikongJueluo	0fbcd915bd	refactor: reorganize RTL files into core/noise subdirectories ... - Move CAM core modules (cam_core_banked, match_engine_pipeline, popcount_pipeline) to hw/rtl/core/ - Move noise modules (cam_read_noise, cam_write_noise, noise_mask_grouped) to hw/rtl/noise/ - Update Makefile include paths and VERILOG_SOURCES to reflect new layout - Update docs/experiments.md file path references - Add sim/results.xml to .gitignore - Bump devenv.lock dependencies	2026-05-14 20:59:46 +08:00