feat(hw): add XNOR-popcount CAM design with cocotb verification

Implement a multi-lane Content Addressable Memory (CAM) that scores
rows by XNOR popcount against a query hash and returns the top-1 match.

RTL modules:
- popcount: parallel group-based population count
- argmax_update: iterative best-match tracking with tie-break
- cam_core: parameterized scanning engine (NUM_ROWS/HASH_BITS/LANES)
  with optional SIM_NOISE and SIM_DEBUG ifdef guards
- cam_top: thin wrapper exposing cam_core ports

Verification:
- Python reference model (ref_model.py) for score-level golden comparison
- cocotb testbench (test_cam_basic.py) covering write/query/reset and
  external noise mask scenarios with score debug verification
- Noise sweep script (sweep_noise.py) measuring top-1 stability under
  configurable bit-flip rates
- Verilator-oriented Makefile with parameterizable compile options

hw/sim/Makefile

@@ -0,0 +1,30 @@
+# Minimal cocotb Makefile.
+# Examples:
+#   make TESTCASE=basic_write_query_no_noise
+#   make TESTCASE=external_noise_mask EXTRA_DEFINES="+define+SIM_NOISE +define+SIM_DEBUG"
+#
+# Verilator is preferred. Icarus may not support all SystemVerilog constructs used here.
+
+SIM ?= verilator
+TOPLEVEL_LANG ?= verilog
+TOPLEVEL := cam_top
+MODULE ?= tests.test_cam_basic
+
+NUM_ROWS ?= 512
+HASH_BITS ?= 512
+LANES ?= 16
+
+EXTRA_ARGS += -DNUM_ROWS=$(NUM_ROWS) -DHASH_BITS=$(HASH_BITS) -DLANES=$(LANES)
+
+# cocotb passes PLUSARGS/EXTRA_ARGS differently across simulators. Keep
+# SystemVerilog parameters explicit through COMPILE_ARGS for Verilator.
+COMPILE_ARGS += -Wall -Wno-fatal
+COMPILE_ARGS += +define+SIM_DEBUG
+COMPILE_ARGS += $(EXTRA_DEFINES)
+
+VERILOG_SOURCES += $(PWD)/../rtl/popcount.sv
+VERILOG_SOURCES += $(PWD)/../rtl/argmax_update.sv
+VERILOG_SOURCES += $(PWD)/../rtl/cam_core.sv
+VERILOG_SOURCES += $(PWD)/../rtl/cam_top.sv
+
+include $(shell cocotb-config --makefiles)/Makefile.sim