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https://github.com/SikongJueluo/Mini-Nav.git
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SikongJueluo
f71bf06484
Implement a multi-lane Content Addressable Memory (CAM) that scores rows by XNOR popcount against a query hash and returns the top-1 match. RTL modules: - popcount: parallel group-based population count - argmax_update: iterative best-match tracking with tie-break - cam_core: parameterized scanning engine (NUM_ROWS/HASH_BITS/LANES) with optional SIM_NOISE and SIM_DEBUG ifdef guards - cam_top: thin wrapper exposing cam_core ports Verification: - Python reference model (ref_model.py) for score-level golden comparison - cocotb testbench (test_cam_basic.py) covering write/query/reset and external noise mask scenarios with score debug verification - Noise sweep script (sweep_noise.py) measuring top-1 stability under configurable bit-flip rates - Verilator-oriented Makefile with parameterizable compile options
31 lines
972 B
Makefile
31 lines
972 B
Makefile
# Minimal cocotb Makefile.
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# Examples:
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# make TESTCASE=basic_write_query_no_noise
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# make TESTCASE=external_noise_mask EXTRA_DEFINES="+define+SIM_NOISE +define+SIM_DEBUG"
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#
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# Verilator is preferred. Icarus may not support all SystemVerilog constructs used here.
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SIM ?= verilator
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TOPLEVEL_LANG ?= verilog
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TOPLEVEL := cam_top
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MODULE ?= tests.test_cam_basic
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NUM_ROWS ?= 512
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HASH_BITS ?= 512
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LANES ?= 16
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EXTRA_ARGS += -DNUM_ROWS=$(NUM_ROWS) -DHASH_BITS=$(HASH_BITS) -DLANES=$(LANES)
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# cocotb passes PLUSARGS/EXTRA_ARGS differently across simulators. Keep
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# SystemVerilog parameters explicit through COMPILE_ARGS for Verilator.
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COMPILE_ARGS += -Wall -Wno-fatal
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COMPILE_ARGS += +define+SIM_DEBUG
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COMPILE_ARGS += $(EXTRA_DEFINES)
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VERILOG_SOURCES += $(PWD)/../rtl/popcount.sv
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VERILOG_SOURCES += $(PWD)/../rtl/argmax_update.sv
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VERILOG_SOURCES += $(PWD)/../rtl/cam_core.sv
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VERILOG_SOURCES += $(PWD)/../rtl/cam_top.sv
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include $(shell cocotb-config --makefiles)/Makefile.sim
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