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refactor(hw/sim): extract common cocotb make infrastructure into shared mk/ directory
- Split monolithic hw/sim/Makefile into modular include files (mk/cocotb-common.mk, mk/rtl-sources.mk) - Add per-module test Makefiles (cam_core_banked, cam_read_noise, cam_write_noise, match_engine_pipeline, perf, top) - Add missing simulation tools (yosys, graphviz, xdot) to devenv.nix - Fix path handling in sweep_noise.py and test modules to be HASH_BITS-aware
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15
hw/sim/tests/modules/cam_write_noise/Makefile
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15
hw/sim/tests/modules/cam_write_noise/Makefile
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SIM_ROOT := $(abspath ../../..)
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RTL_ROOT := $(abspath $(SIM_ROOT)/../rtl)
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include $(SIM_ROOT)/mk/rtl-sources.mk
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TOPLEVEL := cam_write_noise
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COCOTB_TEST_MODULES := tests.modules.cam_write_noise.test_cam_write_noise
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VERILOG_SOURCES := $(RTL_WRITE_NOISE)
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HASH_BITS ?= 512
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WRITE_NOISE_EN ?= 1
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WRITE_NOISE_RATE_NUM ?= 1
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WRITE_NOISE_RATE_DEN ?= 100
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WRITE_NOISE_BITS ?= $(shell echo $$(( $(HASH_BITS) / 64 )))
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include $(SIM_ROOT)/mk/cocotb-common.mk
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