refactor(hw/sim): extract common cocotb make infrastructure into shared mk/ directory

- Split monolithic hw/sim/Makefile into modular include files (mk/cocotb-common.mk, mk/rtl-sources.mk)
- Add per-module test Makefiles (cam_core_banked, cam_read_noise, cam_write_noise, match_engine_pipeline, perf, top)
- Add missing simulation tools (yosys, graphviz, xdot) to devenv.nix
- Fix path handling in sweep_noise.py and test modules to be HASH_BITS-aware

hw/sim/tests/modules/cam_write_noise/Makefile

@@ -0,0 +1,15 @@
+SIM_ROOT := $(abspath ../../..)
+RTL_ROOT := $(abspath $(SIM_ROOT)/../rtl)
+include $(SIM_ROOT)/mk/rtl-sources.mk
+
+TOPLEVEL := cam_write_noise
+COCOTB_TEST_MODULES := tests.modules.cam_write_noise.test_cam_write_noise
+VERILOG_SOURCES := $(RTL_WRITE_NOISE)
+
+HASH_BITS ?= 512
+WRITE_NOISE_EN ?= 1
+WRITE_NOISE_RATE_NUM ?= 1
+WRITE_NOISE_RATE_DEN ?= 100
+WRITE_NOISE_BITS ?= $(shell echo $$(( $(HASH_BITS) / 64 )))
+
+include $(SIM_ROOT)/mk/cocotb-common.mk

hw/sim/tests/modules/cam_write_noise/test_cam_write_noise.py

@@ -0,0 +1,41 @@
+from __future__ import annotations
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from model.ref_model import generate_write_flip_mask
+
+
+async def reset_write_noise(dut):
+    dut.rst_n.value = 0
+    dut.wr_valid.value = 0
+    dut.wr_row.value = 0
+    dut.wr_hash.value = 0
+    for _ in range(3):
+        await RisingEdge(dut.clk)
+    dut.rst_n.value = 1
+    for _ in range(2):
+        await RisingEdge(dut.clk)
+
+
+@cocotb.test()
+async def write_noise_outputs_grouped_noisy_hash(dut):
+    cocotb.start_soon(Clock(dut.clk, 10, unit="ns").start())
+    await reset_write_noise(dut)
+
+    value = 0x123456789ABCDEF
+    dut.wr_row.value = 3
+    dut.wr_hash.value = value
+    dut.wr_valid.value = 1
+    await RisingEdge(dut.clk)
+    dut.wr_valid.value = 0
+
+    while int(dut.core_wr_valid.value) == 0:
+        await RisingEdge(dut.clk)
+
+    seed = 0xB504_F32D_B504_F32D
+    hash_bits = len(dut.wr_hash)
+    noise_bits = hash_bits // 64
+    flip, _ = generate_write_flip_mask((seed << 64) | seed, hash_bits, noise_bits, 1, 100)
+    assert int(dut.core_wr_row.value) == 3
+    assert int(dut.core_wr_hash.value) == (value ^ flip)