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https://github.com/SikongJueluo/Mini-Nav.git
synced 2026-07-12 20:15:31 +08:00
refactor(hw/sim): extract common cocotb make infrastructure into shared mk/ directory
- Split monolithic hw/sim/Makefile into modular include files (mk/cocotb-common.mk, mk/rtl-sources.mk) - Add per-module test Makefiles (cam_core_banked, cam_read_noise, cam_write_noise, match_engine_pipeline, perf, top) - Add missing simulation tools (yosys, graphviz, xdot) to devenv.nix - Fix path handling in sweep_noise.py and test modules to be HASH_BITS-aware
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15
hw/sim/tests/modules/cam_read_noise/Makefile
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15
hw/sim/tests/modules/cam_read_noise/Makefile
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SIM_ROOT := $(abspath ../../..)
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RTL_ROOT := $(abspath $(SIM_ROOT)/../rtl)
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include $(SIM_ROOT)/mk/rtl-sources.mk
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TOPLEVEL := cam_read_noise
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COCOTB_TEST_MODULES := tests.modules.cam_read_noise.test_cam_read_noise
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VERILOG_SOURCES := $(RTL_READ_NOISE)
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HASH_BITS ?= 512
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READ_NOISE_EN ?= 0
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READ_NOISE_RATE_NUM ?= 0
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READ_NOISE_RATE_DEN ?= 100
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READ_NOISE_BITS ?= $(shell echo $$(( $(HASH_BITS) / 64 )))
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include $(SIM_ROOT)/mk/cocotb-common.mk
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0
hw/sim/tests/modules/cam_read_noise/__init__.py
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0
hw/sim/tests/modules/cam_read_noise/__init__.py
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49
hw/sim/tests/modules/cam_read_noise/test_cam_read_noise.py
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hw/sim/tests/modules/cam_read_noise/test_cam_read_noise.py
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from __future__ import annotations
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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async def reset_read_noise(dut):
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dut.rst_n.value = 0
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dut.valid_i.value = 0
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dut.row_ids_i.value = 0
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dut.hashes_i.value = 0
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dut.lane_valid_i.value = 0
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for _ in range(3):
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await RisingEdge(dut.clk)
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dut.rst_n.value = 1
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for _ in range(2):
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await RisingEdge(dut.clk)
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@cocotb.test()
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async def read_noise_disabled_forwards_hashes_after_one_stage(dut):
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cocotb.start_soon(Clock(dut.clk, 10, unit="ns").start())
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await reset_read_noise(dut)
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LANES = len(dut.lane_valid_i)
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ROW_BITS = len(dut.row_ids_i) // LANES
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HASH_BITS_PER_LANE = len(dut.hashes_i) // LANES
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all_lanes_valid = (1 << LANES) - 1
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hashes = 0
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rows = 0
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for lane in range(LANES):
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hashes |= (lane + 0x55) << (lane * HASH_BITS_PER_LANE)
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rows |= lane << (lane * ROW_BITS)
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dut.hashes_i.value = hashes
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dut.row_ids_i.value = rows
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dut.lane_valid_i.value = all_lanes_valid
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dut.valid_i.value = 1
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await RisingEdge(dut.clk)
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dut.valid_i.value = 0
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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assert int(dut.valid_o.value) == 1
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assert int(dut.hashes_noisy_o.value) == hashes
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assert int(dut.row_ids_o.value) == rows
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assert int(dut.lane_valid_o.value) == all_lanes_valid
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