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https://github.com/SikongJueluo/Mini-Nav.git
synced 2026-07-12 20:15:31 +08:00
refactor: reorganize RTL files into core/noise subdirectories
- Move CAM core modules (cam_core_banked, match_engine_pipeline, popcount_pipeline) to hw/rtl/core/ - Move noise modules (cam_read_noise, cam_write_noise, noise_mask_grouped) to hw/rtl/noise/ - Update Makefile include paths and VERILOG_SOURCES to reflect new layout - Update docs/experiments.md file path references - Add sim/results.xml to .gitignore - Bump devenv.lock dependencies
This commit is contained in:
85
hw/rtl/noise/cam_read_noise.sv
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85
hw/rtl/noise/cam_read_noise.sv
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`timescale 1ns / 1ps
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`include "cam_params.svh"
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module cam_read_noise #(
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parameter bit READ_NOISE_EN = 1'b1,
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parameter int READ_NOISE_RATE_NUM = 1,
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parameter int READ_NOISE_RATE_DEN = 100,
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parameter int READ_NOISE_BITS = 8,
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parameter logic [63:0] READ_NOISE_SEED = 64'h6A09_E667_F3BC_C909
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) (
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input logic clk,
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input logic rst_n,
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input logic valid_i,
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input logic [(`LANES)*(`ROW_BITS)-1:0] row_ids_i,
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input logic [(`LANES)*(`HASH_BITS)-1:0] hashes_i,
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input logic [(`LANES)-1:0] lane_valid_i,
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output logic valid_o,
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output logic [(`LANES)*(`ROW_BITS)-1:0] row_ids_o,
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output logic [(`LANES)*(`HASH_BITS)-1:0] hashes_noisy_o,
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output logic [(`LANES)-1:0] lane_valid_o
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);
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logic valid_q;
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logic [(`LANES)*(`ROW_BITS)-1:0] row_ids_q;
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logic [(`LANES)*(`HASH_BITS)-1:0] hashes_q;
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logic [(`LANES)-1:0] lane_valid_q;
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logic [127:0] random_num [0:`LANES-1];
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logic [(`HASH_BITS)-1:0] mask [0:`LANES-1];
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initial begin
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if (READ_NOISE_SEED == 64'd0) $fatal(1, "READ_NOISE_SEED must be nonzero");
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end
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generate
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for (genvar lane = 0; lane < `LANES; lane++) begin : gen_lane_noise
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localparam logic [63:0] LANE_SALT = 64'(lane + 1) * 64'h9E37_79B9_7F4A_7C15;
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random128 u_random_read (
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.clk (clk),
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.rst_n (rst_n),
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.enable(valid_i && lane_valid_i[lane] && READ_NOISE_EN && (READ_NOISE_RATE_NUM > 0)),
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.seed ({(READ_NOISE_SEED ^ LANE_SALT), (READ_NOISE_SEED ^ LANE_SALT)}),
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.out (random_num[lane])
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);
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noise_mask_grouped #(
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.HASH_BITS (`HASH_BITS),
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.NOISE_BITS (READ_NOISE_BITS),
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.NOISE_RATE_NUM (READ_NOISE_RATE_NUM),
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.NOISE_RATE_DEN (READ_NOISE_RATE_DEN)
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) u_mask (
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.random_i(random_num[lane]),
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.mask_o (mask[lane])
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);
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end
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endgenerate
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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valid_q <= 1'b0;
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row_ids_q <= '0;
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hashes_q <= '0;
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lane_valid_q <= '0;
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valid_o <= 1'b0;
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row_ids_o <= '0;
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hashes_noisy_o <= '0;
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lane_valid_o <= '0;
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end else begin
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valid_q <= valid_i;
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row_ids_q <= row_ids_i;
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hashes_q <= hashes_i;
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lane_valid_q <= lane_valid_i;
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valid_o <= valid_q;
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row_ids_o <= row_ids_q;
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lane_valid_o <= lane_valid_q;
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for (int lane = 0; lane < `LANES; lane++) begin
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if (READ_NOISE_EN && (READ_NOISE_RATE_NUM > 0) && lane_valid_q[lane]) begin
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hashes_noisy_o[lane*`HASH_BITS +: `HASH_BITS] <= hashes_q[lane*`HASH_BITS +: `HASH_BITS] ^ mask[lane];
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end else begin
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hashes_noisy_o[lane*`HASH_BITS +: `HASH_BITS] <= hashes_q[lane*`HASH_BITS +: `HASH_BITS];
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end
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end
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end
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end
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endmodule
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75
hw/rtl/noise/cam_write_noise.sv
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75
hw/rtl/noise/cam_write_noise.sv
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`timescale 1ns / 1ps
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`include "cam_params.svh"
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module cam_write_noise #(
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parameter bit WRITE_NOISE_EN = 1'b1,
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parameter int WRITE_NOISE_RATE_NUM = 1,
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parameter int WRITE_NOISE_RATE_DEN = 100,
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parameter int WRITE_NOISE_BITS = 8,
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parameter logic [63:0] WRITE_NOISE_SEED = 64'hB504_F32D_B504_F32D
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) (
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input logic clk,
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input logic rst_n,
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input logic wr_valid,
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output logic wr_ready,
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input logic [(`ROW_BITS)-1:0] wr_row,
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input logic [(`HASH_BITS)-1:0] wr_hash,
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output logic core_wr_valid,
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output logic [(`ROW_BITS)-1:0] core_wr_row,
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output logic [(`HASH_BITS)-1:0] core_wr_hash
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);
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logic pending_q;
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logic [(`ROW_BITS)-1:0] row_q;
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logic [(`HASH_BITS)-1:0] hash_q;
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logic [127:0] random_num;
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logic [(`HASH_BITS)-1:0] flip_mask;
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assign wr_ready = !pending_q;
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random128 u_random_write (
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.clk (clk),
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.rst_n (rst_n),
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.enable(wr_valid && wr_ready && WRITE_NOISE_EN && (WRITE_NOISE_RATE_NUM > 0)),
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.seed ({WRITE_NOISE_SEED, WRITE_NOISE_SEED}),
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.out (random_num)
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);
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noise_mask_grouped #(
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.HASH_BITS (`HASH_BITS),
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.NOISE_BITS (WRITE_NOISE_BITS),
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.NOISE_RATE_NUM (WRITE_NOISE_RATE_NUM),
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.NOISE_RATE_DEN (WRITE_NOISE_RATE_DEN)
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) u_mask (
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.random_i(random_num),
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.mask_o (flip_mask)
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);
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initial begin
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if (WRITE_NOISE_SEED == 64'd0) $fatal(1, "WRITE_NOISE_SEED must be nonzero");
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end
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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pending_q <= 1'b0;
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row_q <= '0;
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hash_q <= '0;
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core_wr_valid <= 1'b0;
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core_wr_row <= '0;
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core_wr_hash <= '0;
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end else begin
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core_wr_valid <= pending_q;
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core_wr_row <= row_q;
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if (WRITE_NOISE_EN && (WRITE_NOISE_RATE_NUM > 0)) begin
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core_wr_hash <= hash_q ^ flip_mask;
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end else begin
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core_wr_hash <= hash_q;
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end
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pending_q <= wr_valid && wr_ready;
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if (wr_valid && wr_ready) begin
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row_q <= wr_row;
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hash_q <= wr_hash;
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end
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end
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end
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endmodule
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37
hw/rtl/noise/noise_mask_grouped.sv
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37
hw/rtl/noise/noise_mask_grouped.sv
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@@ -0,0 +1,37 @@
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`timescale 1ns / 1ps
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`include "cam_params.svh"
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module noise_mask_grouped #(
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parameter int HASH_BITS = `HASH_BITS,
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parameter int NOISE_BITS = 8,
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parameter int NOISE_RATE_NUM = 1,
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parameter int NOISE_RATE_DEN = 100
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) (
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input logic [127:0] random_i,
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output logic [HASH_BITS-1:0] mask_o
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);
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localparam int GROUP_BITS = HASH_BITS / NOISE_BITS;
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localparam int BIT_INDEX_BITS = 6;
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localparam int SAMPLE_BITS = 8;
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localparam int GROUP_RAND_BITS = BIT_INDEX_BITS + SAMPLE_BITS;
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localparam int SAMPLE_RANGE = 1 << SAMPLE_BITS;
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localparam int THRESHOLD = (NOISE_RATE_NUM * SAMPLE_RANGE) / NOISE_RATE_DEN;
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initial begin
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if (NOISE_BITS <= 0) $fatal(1, "NOISE_BITS must be > 0");
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if (HASH_BITS % NOISE_BITS != 0) $fatal(1, "HASH_BITS must be divisible by NOISE_BITS");
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if (GROUP_BITS != 64) $fatal(1, "GROUP_BITS must be 64 for 6-bit grouped noise");
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if (NOISE_BITS * GROUP_RAND_BITS > 128) $fatal(1, "NOISE_BITS consumes more than 128 random bits");
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if (NOISE_RATE_DEN <= 0) $fatal(1, "NOISE_RATE_DEN must be > 0");
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if (NOISE_RATE_NUM < 0 || NOISE_RATE_NUM > NOISE_RATE_DEN) $fatal(1, "NOISE_RATE_NUM out of range");
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end
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always_comb begin
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mask_o = '0;
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for (int i = 0; i < NOISE_BITS; i++) begin
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if (random_i[i * GROUP_RAND_BITS + BIT_INDEX_BITS +: SAMPLE_BITS] < THRESHOLD) begin
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mask_o[i * GROUP_BITS + random_i[i * GROUP_RAND_BITS +: BIT_INDEX_BITS]] = 1'b1;
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end
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end
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end
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endmodule
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