diff --git a/devenv.lock b/devenv.lock index 69dae25..f17121a 100644 --- a/devenv.lock +++ b/devenv.lock @@ -3,11 +3,11 @@ "devenv": { "locked": { "dir": "src/modules", - "lastModified": 1773767086, - "narHash": "sha256-3eKyl4LXswf6P17/u59x8oQXDgCfYX+UX0uh7YHFwJc=", + "lastModified": 1778705971, + "narHash": "sha256-n0LjnKBAjJ5/mgNzOCeVvAeHUrNMUZ3fBQx/UDCkHtQ=", "owner": "cachix", "repo": "devenv", - "rev": "a5e5a7f8b1c9a7f33f9d82192b692768b39ec710", + "rev": "64d4353a3628c4138c84d8ba10987da2ba27fddd", "type": "github" }, "original": { @@ -61,11 +61,11 @@ "nixpkgs-src": "nixpkgs-src" }, "locked": { - "lastModified": 1773704619, - "narHash": "sha256-LKtmit8Sr81z8+N2vpIaN/fyiQJ8f7XJ6tMSKyDVQ9s=", + "lastModified": 1778507786, + "narHash": "sha256-HzSQCKMsMr8r55LwM1JuzIOB+8bzk0FEv6sItKvsfoY=", "owner": "cachix", "repo": "devenv-nixpkgs", - "rev": "906534d75b0e2fe74a719559dfb1ad3563485f43", + "rev": "8f24a228a782e24576b155d1e39f0d914b380691", "type": "github" }, "original": { @@ -78,11 +78,11 @@ "nixpkgs-src": { "flake": false, "locked": { - "lastModified": 1773597492, - "narHash": "sha256-hQ284SkIeNaeyud+LS0WVLX+WL2rxcVZLFEaK0e03zg=", + "lastModified": 1778274207, + "narHash": "sha256-I4puXmX1iovcCHZlRmztO3vW0mAbbRvq4F8wgIMQ1MM=", "owner": "NixOS", "repo": "nixpkgs", - "rev": "a07d4ce6bee67d7c838a8a5796e75dff9caa21ef", + "rev": "b3da656039dc7a6240f27b2ef8cc6a3ef3bccae7", "type": "github" }, "original": { diff --git a/docs/experiments.md b/docs/experiments.md index b3886fb..0b22dd5 100644 --- a/docs/experiments.md +++ b/docs/experiments.md @@ -26,12 +26,12 @@ - `hw/rtl/cam_top.sv` - `hw/rtl/cam_noisy.sv` -- `hw/rtl/cam_core_banked.sv` -- `hw/rtl/match_engine_pipeline.sv` -- `hw/rtl/popcount_pipeline.sv` -- `hw/rtl/cam_write_noise.sv` -- `hw/rtl/cam_read_noise.sv` -- `hw/rtl/noise_mask_grouped.sv` +- `hw/rtl/core/cam_core_banked.sv` +- `hw/rtl/core/match_engine_pipeline.sv` +- `hw/rtl/core/popcount_pipeline.sv` +- `hw/rtl/noise/cam_write_noise.sv` +- `hw/rtl/noise/cam_read_noise.sv` +- `hw/rtl/noise/noise_mask_grouped.sv` - `hw/rtl/cam_params.svh` - `hw/sim/model/ref_model.py` - `hw/sim/sweep_noise.py` @@ -127,9 +127,9 @@ ### 已具备内容 -- 写入/读取:`hw/rtl/cam_core_banked.sv`、`hw/sim/tests/test_cam_core_banked.py` -- 匹配与 popcount:`hw/rtl/match_engine_pipeline.sv`、`hw/rtl/popcount_pipeline.sv` -- 噪声模块:`hw/rtl/cam_write_noise.sv`、`hw/rtl/cam_read_noise.sv` +- 写入/读取:`hw/rtl/core/cam_core_banked.sv`、`hw/sim/tests/test_cam_core_banked.py` +- 匹配与 popcount:`hw/rtl/core/match_engine_pipeline.sv`、`hw/rtl/core/popcount_pipeline.sv` +- 噪声模块:`hw/rtl/noise/cam_write_noise.sv`、`hw/rtl/noise/cam_read_noise.sv` - 参考模型:`hw/sim/model/ref_model.py` - 集成测试:`hw/sim/tests/test_cam_basic.py` diff --git a/hw/.gitignore b/hw/.gitignore index e141516..179b494 100644 --- a/hw/.gitignore +++ b/hw/.gitignore @@ -1 +1,2 @@ sim/sim_build +sim/results.xml diff --git a/hw/rtl/cam_core_banked.sv b/hw/rtl/core/cam_core_banked.sv similarity index 100% rename from hw/rtl/cam_core_banked.sv rename to hw/rtl/core/cam_core_banked.sv diff --git a/hw/rtl/match_engine_pipeline.sv b/hw/rtl/core/match_engine_pipeline.sv similarity index 100% rename from hw/rtl/match_engine_pipeline.sv rename to hw/rtl/core/match_engine_pipeline.sv diff --git a/hw/rtl/popcount_pipeline.sv b/hw/rtl/core/popcount_pipeline.sv similarity index 100% rename from hw/rtl/popcount_pipeline.sv rename to hw/rtl/core/popcount_pipeline.sv diff --git a/hw/rtl/cam_read_noise.sv b/hw/rtl/noise/cam_read_noise.sv similarity index 100% rename from hw/rtl/cam_read_noise.sv rename to hw/rtl/noise/cam_read_noise.sv diff --git a/hw/rtl/cam_write_noise.sv b/hw/rtl/noise/cam_write_noise.sv similarity index 100% rename from hw/rtl/cam_write_noise.sv rename to hw/rtl/noise/cam_write_noise.sv diff --git a/hw/rtl/noise_mask_grouped.sv b/hw/rtl/noise/noise_mask_grouped.sv similarity index 100% rename from hw/rtl/noise_mask_grouped.sv rename to hw/rtl/noise/noise_mask_grouped.sv diff --git a/hw/sim/Makefile b/hw/sim/Makefile index ef139df..489f0ba 100644 --- a/hw/sim/Makefile +++ b/hw/sim/Makefile @@ -11,7 +11,7 @@ LANES ?= 8 EXTRA_ARGS += +define+NUM_ROWS=$(NUM_ROWS) +define+HASH_BITS=$(HASH_BITS) +define+LANES=$(LANES) COMPILE_ARGS += -Wall -Wno-fatal -COMPILE_ARGS += -I$(PWD)/../rtl +COMPILE_ARGS += -I$(PWD)/../rtl -I$(PWD)/../rtl/core -I$(PWD)/../rtl/noise COMPILE_ARGS += +define+SIM_DEBUG COMPILE_ARGS += $(EXTRA_DEFINES) @@ -66,12 +66,12 @@ COMPILE_ARGS += -Wno-UNOPTFLAT endif VERILOG_SOURCES += $(PWD)/../rtl/random/random128.sv -VERILOG_SOURCES += $(PWD)/../rtl/noise_mask_grouped.sv -VERILOG_SOURCES += $(PWD)/../rtl/cam_core_banked.sv -VERILOG_SOURCES += $(PWD)/../rtl/cam_write_noise.sv -VERILOG_SOURCES += $(PWD)/../rtl/cam_read_noise.sv -VERILOG_SOURCES += $(PWD)/../rtl/popcount_pipeline.sv -VERILOG_SOURCES += $(PWD)/../rtl/match_engine_pipeline.sv +VERILOG_SOURCES += $(PWD)/../rtl/noise/noise_mask_grouped.sv +VERILOG_SOURCES += $(PWD)/../rtl/core/cam_core_banked.sv +VERILOG_SOURCES += $(PWD)/../rtl/noise/cam_write_noise.sv +VERILOG_SOURCES += $(PWD)/../rtl/noise/cam_read_noise.sv +VERILOG_SOURCES += $(PWD)/../rtl/core/popcount_pipeline.sv +VERILOG_SOURCES += $(PWD)/../rtl/core/match_engine_pipeline.sv VERILOG_SOURCES += $(PWD)/../rtl/cam_noisy.sv VERILOG_SOURCES += $(PWD)/../rtl/cam_top.sv