refactor: reorganize RTL files into core/noise subdirectories

- Move CAM core modules (cam_core_banked, match_engine_pipeline, popcount_pipeline) to hw/rtl/core/
- Move noise modules (cam_read_noise, cam_write_noise, noise_mask_grouped) to hw/rtl/noise/
- Update Makefile include paths and VERILOG_SOURCES to reflect new layout
- Update docs/experiments.md file path references
- Add sim/results.xml to .gitignore
- Bump devenv.lock dependencies

hw/.gitignore

@@ -1 +1,2 @@
 sim/sim_build
+sim/results.xml

hw/sim/Makefile

@@ -11,7 +11,7 @@ LANES ?= 8
 EXTRA_ARGS += +define+NUM_ROWS=$(NUM_ROWS) +define+HASH_BITS=$(HASH_BITS) +define+LANES=$(LANES)
 
 COMPILE_ARGS += -Wall -Wno-fatal
-COMPILE_ARGS += -I$(PWD)/../rtl
+COMPILE_ARGS += -I$(PWD)/../rtl -I$(PWD)/../rtl/core -I$(PWD)/../rtl/noise
 COMPILE_ARGS += +define+SIM_DEBUG
 COMPILE_ARGS += $(EXTRA_DEFINES)
 
@@ -66,12 +66,12 @@ COMPILE_ARGS += -Wno-UNOPTFLAT
 endif
 
 VERILOG_SOURCES += $(PWD)/../rtl/random/random128.sv
-VERILOG_SOURCES += $(PWD)/../rtl/noise_mask_grouped.sv
-VERILOG_SOURCES += $(PWD)/../rtl/cam_core_banked.sv
-VERILOG_SOURCES += $(PWD)/../rtl/cam_write_noise.sv
-VERILOG_SOURCES += $(PWD)/../rtl/cam_read_noise.sv
-VERILOG_SOURCES += $(PWD)/../rtl/popcount_pipeline.sv
-VERILOG_SOURCES += $(PWD)/../rtl/match_engine_pipeline.sv
+VERILOG_SOURCES += $(PWD)/../rtl/noise/noise_mask_grouped.sv
+VERILOG_SOURCES += $(PWD)/../rtl/core/cam_core_banked.sv
+VERILOG_SOURCES += $(PWD)/../rtl/noise/cam_write_noise.sv
+VERILOG_SOURCES += $(PWD)/../rtl/noise/cam_read_noise.sv
+VERILOG_SOURCES += $(PWD)/../rtl/core/popcount_pipeline.sv
+VERILOG_SOURCES += $(PWD)/../rtl/core/match_engine_pipeline.sv
 VERILOG_SOURCES += $(PWD)/../rtl/cam_noisy.sv
 VERILOG_SOURCES += $(PWD)/../rtl/cam_top.sv