refactor: reorganize RTL files into core/noise subdirectories

- Move CAM core modules (cam_core_banked, match_engine_pipeline, popcount_pipeline) to hw/rtl/core/
- Move noise modules (cam_read_noise, cam_write_noise, noise_mask_grouped) to hw/rtl/noise/
- Update Makefile include paths and VERILOG_SOURCES to reflect new layout
- Update docs/experiments.md file path references
- Add sim/results.xml to .gitignore
- Bump devenv.lock dependencies

docs/experiments.md

@@ -26,12 +26,12 @@
 
 - `hw/rtl/cam_top.sv`
 - `hw/rtl/cam_noisy.sv`
-- `hw/rtl/cam_core_banked.sv`
-- `hw/rtl/match_engine_pipeline.sv`
-- `hw/rtl/popcount_pipeline.sv`
-- `hw/rtl/cam_write_noise.sv`
-- `hw/rtl/cam_read_noise.sv`
-- `hw/rtl/noise_mask_grouped.sv`
+- `hw/rtl/core/cam_core_banked.sv`
+- `hw/rtl/core/match_engine_pipeline.sv`
+- `hw/rtl/core/popcount_pipeline.sv`
+- `hw/rtl/noise/cam_write_noise.sv`
+- `hw/rtl/noise/cam_read_noise.sv`
+- `hw/rtl/noise/noise_mask_grouped.sv`
 - `hw/rtl/cam_params.svh`
 - `hw/sim/model/ref_model.py`
 - `hw/sim/sweep_noise.py`
@@ -127,9 +127,9 @@
 
 ### 已具备内容
 
-- 写入/读取：`hw/rtl/cam_core_banked.sv`、`hw/sim/tests/test_cam_core_banked.py`
-- 匹配与 popcount：`hw/rtl/match_engine_pipeline.sv`、`hw/rtl/popcount_pipeline.sv`
-- 噪声模块：`hw/rtl/cam_write_noise.sv`、`hw/rtl/cam_read_noise.sv`
+- 写入/读取：`hw/rtl/core/cam_core_banked.sv`、`hw/sim/tests/test_cam_core_banked.py`
+- 匹配与 popcount：`hw/rtl/core/match_engine_pipeline.sv`、`hw/rtl/core/popcount_pipeline.sv`
+- 噪声模块：`hw/rtl/noise/cam_write_noise.sv`、`hw/rtl/noise/cam_read_noise.sv`
 - 参考模型：`hw/sim/model/ref_model.py`
 - 集成测试：`hw/sim/tests/test_cam_basic.py`