feat(hw/rtl): add xorshift PRNG modules and refactor cam_noisy FSM

- Add random32, random64 and random128 xorshift PRNG modules
- Refactor cam_noisy FSM: split state register, next-state logic, and datapath into distinct blocks
- Rename state_q/state_d to curr_state/next_state for clarity
- Add MASK_GROUPS localparam and fix type casting in noise generation
- Update .gitignore to exclude docs/superpowers
This commit is contained in:
2026-05-04 18:03:07 +08:00
parent 2da17e101b
commit 0dd01fb1b7
5 changed files with 144 additions and 22 deletions

28
hw/rtl/random/random64.sv Normal file
View File

@@ -0,0 +1,28 @@
`timescale 1ns / 1ps
module random64 (
input logic clk,
input logic rst_n,
input logic enable,
input logic [63:0] seed,
output logic [63:0] out
);
function automatic logic [63:0] xorshift64(input logic [63:0] x);
logic [63:0] s;
s = x;
s ^= s << 13;
s ^= s >> 7;
s ^= s << 17;
return s;
endfunction
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
out <= seed;
end else if (enable) begin
out <= xorshift64(out);
end
end
endmodule