244 lines
8.7 KiB
Markdown
244 lines
8.7 KiB
Markdown
# 基础-3-数码管实验
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---
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在许多项目设计中，我们通常需要一些显示设备来显示我们需要的信息，可以选择的显示设备有很多，而数码管是使用最多，最简单的显示设备之一。
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## 3.1 章节导读
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本章将通过数码管驱动实验讲解FPGA数字系统中重要的"选通控制"概念。读者将学习到：
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1. 数码管工作原理与动态扫描技术
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2. 多路复用（Multiplexing）设计方法
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3. 参数化模块设计技巧
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4. 外设驱动时序规划
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5. ASCII到段码的转换原理
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实验将使用Verilog HDL实现一个支持8位数码管显示、包含字符动态滚动和选通控制的完整系统。
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## 3.2 理论学习
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### 3.2.1 数码管结构
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- 7段数码管组成：A-G段+DP小数点
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- 共阳/共阴类型区分（本实验采用共阳型，低电平有效）
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### 3.2.2 动态扫描原理
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```
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显示周期 = 刷新周期 × 数码管数量
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人眼视觉暂留效应（>60Hz）
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扫描频率计算公式：f_scan = f_clk / CLK_CYCLE
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```
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### 3.2.3 关键技术
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- 时分复用：分时选通数码管
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- 段码生成：ASCII字符到七段码转换
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- 消隐处理：消除切换时的视觉残留
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### 3.2.4 设计指标
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| 参数 | 值 | 说明 |
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|-------|-----|-------------------|
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| 位数 | 8 | 数码管数量 |
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| 频率 | 200Hz | 单管刷新频率 |
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| 分辨率 | 8bit | 段码控制（含小数点）|
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## 3.2 实战演练
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### 3.3.1 系统架构
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```verilog
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系统框图：
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[Top模块] → [显示驱动模块] → [选通控制模块]
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↖ ASCII数据生成 ↙ 时钟分频
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```
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### 3.3.2 模块设计
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#### led_display_selector
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```verilog
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module led_display_selector #(
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parameter NUM = 4,
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parameter VALID_SIGNAL = 1'b0,
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parameter CLK_CYCLE = 1000
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)(
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input wire clk,
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input wire rstn,
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input wire [NUM*8-1:0] led_in,
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output reg [7:0] led_display_seg,//[DP,G,F,E,D,C,B,A]
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output reg [NUM-1:0] led_display_sel
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);
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reg [31:0] clk_cnt;
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always @(posedge clk or negedge rstn) begin
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if (!rstn) clk_cnt <= 0;
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else if(clk_cnt == CLK_CYCLE) clk_cnt <= 0;
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else clk_cnt <= clk_cnt + 1;
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end
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wire seg_change = (clk_cnt == CLK_CYCLE) ? 1'b1 : 1'b0;
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always @(posedge clk or negedge rstn) begin
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if(!rstn) led_display_sel <= {{(NUM-1){~VALID_SIGNAL}}, VALID_SIGNAL};
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else if (seg_change) led_display_sel <= {led_display_sel[NUM-2:0], led_display_sel[NUM-1]};
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else led_display_sel <= led_display_sel;
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end
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integer i;
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always @(*) begin
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for(i=0;i<NUM;i=i+1) begin
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if(led_display_sel[NUM-1-i] == VALID_SIGNAL)
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led_display_seg = led_in[i*8 +: 8] ^ ({8{~VALID_SIGNAL}});
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end
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end
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endmodule //led_display_ctrl
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```
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#### led_display_driver
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```verilog
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module led_display_driver(// 8个数码管显示，阳极管（在selector中已经做了阴阳处理）
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input wire clk,
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input wire rstn,
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input wire [8*8-1:0] assic_seg, //ASSIC coding
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input wire [7:0] seg_point, //显示小数点
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output wire [7:0] led_display_seg,
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output wire [7:0] led_display_sel
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);
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reg [8*8-1:0] led_in;
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integer i;
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always @(*) begin
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led_in = 0;
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for(i=0;i<8;i=i+1) begin //led_in[i*8 +: 8] <---> assic_seg[i*8 +: 8]
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case (assic_seg[i*8 +: 8])
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"0": led_in[i*8 +: 8] = (8'h3f) | {seg_point[i],7'b0};
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"1": led_in[i*8 +: 8] = (8'h06) | {seg_point[i],7'b0};
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"2": led_in[i*8 +: 8] = (8'h5b) | {seg_point[i],7'b0};
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"3": led_in[i*8 +: 8] = (8'h4f) | {seg_point[i],7'b0};
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"4": led_in[i*8 +: 8] = (8'h66) | {seg_point[i],7'b0};
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"5": led_in[i*8 +: 8] = (8'h6d) | {seg_point[i],7'b0};
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"6": led_in[i*8 +: 8] = (8'h7d) | {seg_point[i],7'b0};
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"7": led_in[i*8 +: 8] = (8'h07) | {seg_point[i],7'b0};
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"8": led_in[i*8 +: 8] = (8'h7f) | {seg_point[i],7'b0};
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"9": led_in[i*8 +: 8] = (8'h6f) | {seg_point[i],7'b0};
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"A","a": led_in[i*8 +: 8] = (8'h77) | {seg_point[i],7'b0};
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"B","b": led_in[i*8 +: 8] = (8'h7c) | {seg_point[i],7'b0};
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"C","c": led_in[i*8 +: 8] = (8'h39) | {seg_point[i],7'b0};
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"D","d": led_in[i*8 +: 8] = (8'h5e) | {seg_point[i],7'b0};
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"E","e": led_in[i*8 +: 8] = (8'h79) | {seg_point[i],7'b0};
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"F","f": led_in[i*8 +: 8] = (8'h71) | {seg_point[i],7'b0};
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"G","g": led_in[i*8 +: 8] = (8'h3d) | {seg_point[i],7'b0};
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"H","h": led_in[i*8 +: 8] = (8'h76) | {seg_point[i],7'b0};
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"I","i": led_in[i*8 +: 8] = (8'h0f) | {seg_point[i],7'b0};
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"J","j": led_in[i*8 +: 8] = (8'h0e) | {seg_point[i],7'b0};
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"K","k": led_in[i*8 +: 8] = (8'h75) | {seg_point[i],7'b0};
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"L","l": led_in[i*8 +: 8] = (8'h38) | {seg_point[i],7'b0};
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"M","m": led_in[i*8 +: 8] = (8'h37) | {seg_point[i],7'b0};
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"N","n": led_in[i*8 +: 8] = (8'h54) | {seg_point[i],7'b0};
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"O","o": led_in[i*8 +: 8] = (8'h5c) | {seg_point[i],7'b0};
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"P","p": led_in[i*8 +: 8] = (8'h73) | {seg_point[i],7'b0};
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"Q","q": led_in[i*8 +: 8] = (8'h67) | {seg_point[i],7'b0};
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"R","r": led_in[i*8 +: 8] = (8'h31) | {seg_point[i],7'b0};
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"S","s": led_in[i*8 +: 8] = (8'h49) | {seg_point[i],7'b0};
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"T","t": led_in[i*8 +: 8] = (8'h78) | {seg_point[i],7'b0};
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"U","u": led_in[i*8 +: 8] = (8'h3e) | {seg_point[i],7'b0};
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"V","v": led_in[i*8 +: 8] = (8'h1c) | {seg_point[i],7'b0};
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"W","w": led_in[i*8 +: 8] = (8'h7e) | {seg_point[i],7'b0};
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"X","x": led_in[i*8 +: 8] = (8'h64) | {seg_point[i],7'b0};
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"Y","y": led_in[i*8 +: 8] = (8'h6e) | {seg_point[i],7'b0};
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"Z","z": led_in[i*8 +: 8] = (8'h59) | {seg_point[i],7'b0};
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" ": led_in[i*8 +: 8] = (8'h00) | {seg_point[i],7'b0};
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"-": led_in[i*8 +: 8] = (8'h40) | {seg_point[i],7'b0};
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"_": led_in[i*8 +: 8] = (8'h08) | {seg_point[i],7'b0};
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"=": led_in[i*8 +: 8] = (8'h48) | {seg_point[i],7'b0};
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"+": led_in[i*8 +: 8] = (8'h5c) | {seg_point[i],7'b0};
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"(": led_in[i*8 +: 8] = (8'h39) | {seg_point[i],7'b0};
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")": led_in[i*8 +: 8] = (8'h0F) | {seg_point[i],7'b0};
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default: led_in[i*8 +: 8] = (8'h00) | {seg_point[i],7'b0};
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endcase
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end
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end
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led_display_selector #(
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.NUM ( 8 ),
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.VALID_SIGNAL ( 1'b0 ), //阳极管，低电平亮
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.CLK_CYCLE ( 5000 ))
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u_led_display_selector(
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.clk ( clk ),
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.rstn ( rstn ),
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.led_in ( led_in ),
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.led_display_seg ( led_display_seg ),
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.led_display_sel ( led_display_sel )
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);
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endmodule //moduleName
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```
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#### led_display_top
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```verilog
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module led_diaplay_top(
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//system io
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input wire external_clk ,
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input wire external_rstn,
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//led display io
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output wire [7:0] led_display_seg,
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output wire [7:0] led_display_sel
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);
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reg [43*8-1:0] assic_seg;
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reg [7:0] seg_point;
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reg [31:0] clk_cnt;
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always @(posedge external_clk or negedge external_rstn) begin
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if(!external_rstn) clk_cnt <= 0;
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else clk_cnt <= clk_cnt + 1;
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end
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always @(posedge external_clk or negedge external_rstn) begin
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if(!external_rstn) begin
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assic_seg <= "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ -_=+()";
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seg_point <= 8'b00000001;
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end else if({clk_cnt[24]==1'b1} && (clk_cnt[23:0]==25'b0))begin
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assic_seg <= {assic_seg[8*43-8-1:0], assic_seg[8*43-1 -: 8]};
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seg_point <= {seg_point[6:0], seg_point[7]};
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end else begin
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assic_seg <= assic_seg;
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seg_point <= seg_point;
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end
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end
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led_display_driver u_led_display_driver(
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.clk ( external_clk ),
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.rstn ( external_rstn ),
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.assic_seg ( assic_seg[8*43-1 -: 8*8] ),
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.seg_point ( seg_point ),
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.led_display_seg ( led_display_seg ),
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.led_display_sel ( led_display_sel )
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);
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endmodule //led_diaplay_top
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```
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### 3.3.3 上板验证步骤
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1. 设置参数：CLK_CYCLE=5000（对应200Hz扫描频率）
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2. 绑定管脚：连接数码管段选/位选信号
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3. 观察现象：字符"01234567"应稳定显示
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4. 修改assic_seg初始值验证滚动功能
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---
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## 3.4 章末总结
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**关键收获：**
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1. 掌握动态扫描消除器件闪烁的原理
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2. 理解参数化设计（NUM/VALID_SIGNAL）的优势
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3. 学习时序控制中计数器的重要作用
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4. 实践ASCII到硬件编码的转换方法
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**设计亮点：**
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- 支持阴阳极自动适配（通过VALID_SIGNAL参数）
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- 字符环形缓冲区实现无缝滚动
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- 参数化设计增强模块复用性
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---
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## 3.5 拓展训练
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结合流水灯实验和数码管实验：数码管显示数字，标识出当前流水到了哪一个灯 |