SikongJueluo

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• Joined on 2024-03-24

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4

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SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-15 16:36:21 +08:00

b139542c4c fix: 添加互斥锁，并增加更多log输出

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-15 14:26:28 +08:00

be8fed995c feat: 使用排序来解决时间冲突

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-15 11:30:16 +08:00

49cbdc51d9 fix: 修复多个外设无法认证的问题

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-14 17:27:12 +08:00

89cc2291c0 fix: 管理员无法通过认证固化比特流文件的问题

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-14 17:13:57 +08:00

6500c1ce2d fix: 使用互斥锁确保数据写入的顺序性

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-14 16:42:35 +08:00

c9fc6961fa feat: 持续完善逻辑分析仪的界面

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-14 16:07:43 +08:00

4d6c06a0e0 feat: 添加逻辑分析仪

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-14 14:02:28 +08:00

e8a16fd446 fix: udp实现11端口

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-14 14:01:12 +08:00

ca906489c2 feat: 实现udp多端口

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-14 13:30:23 +08:00

2894ee24be feat: 实现udp并发接受数据？？

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-14 12:15:56 +08:00

6068a10d67 feat: not finish logic analyzer ui

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-13 19:42:12 +08:00

1273be7dee feat: 完成logicanalyzer的api

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-13 16:55:45 +08:00

78737f6839 feat: 删除无用数据与冗余逻辑以提升性能

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-13 16:00:55 +08:00

e38770a496 fix: 删除无用函数与信号，修复全屏bug

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-13 14:48:24 +08:00

a76ee74656 feat：减少冗余代码？？？

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-13 13:53:33 +08:00

8221f8e133 feat: 使用发送多个地址包来改善大数据读取的速度

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-13 13:28:49 +08:00

bad64bdfbd fix: 优化界面，解耦组件抽屉

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-13 11:40:44 +08:00

32b126b93f feat: 添加大数据接收方法，以提高接受速度

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-13 10:58:54 +08:00

b913f58f13 feat: udpServer使用异步处理数据包

SikongJueluo pushed to master at SikongJueluo/FPGA_WebLab 2025-07-12 21:56:05 +08:00

eebc5105a0 feat: 画布解耦合