Files
Mini-Nav/hw/rtl/cam_params.svh
SikongJueluo 8f59a287c4 feat(hw): add banked CAM pipeline with grouped read/write noise
- Add cam_core_banked.sv with 8-lane banked CAM core
- Add cam_write_noise.sv and cam_read_noise.sv for grouped noise injection
- Add noise_mask_grouped.sv generating grouped flip masks from 128-bit PRNG
- Add match_engine_pipeline.sv with multi-stage pipelined top-1 selection
- Add popcount_pipeline.sv for pipelined popcount operations
- Refactor test_cam_basic.py with parametrized DUT introspection helpers
- Add Python ref_model match_top1_with_read_noise() for read noise verification
- Update Makefile with separate WRITE_NOISE_* and READ_NOISE_* parameter groups
- Add new testbenches: test_cam_core_banked, test_cam_read_noise,
  test_cam_write_noise, test_match_engine_pipeline, test_ref_model_noise
  
breaking change hint: NUM_ROWS default changed from 512→4096, LANES from 16→8
2026-05-13 18:22:28 +08:00

55 lines
1.8 KiB
Systemverilog

//==============================================================================
// CAM Parameter Definitions
//==============================================================================
// This file defines shared compile-time parameters for the Content-Addressable
// Memory (CAM) subsystem. All `define macros use `ifndef guards to allow
// command-line override via +define+.
//
// Macros:
// NUM_ROWS — Number of rows in the CAM array
// HASH_BITS — Width of the hash value in bits
// LANES — Number of parallel comparison lanes
// ROW_BITS — Bits needed to index NUM_ROWS rows ($clog2(NUM_ROWS))
// SCORE_BITS — Bits needed to represent HASH_BITS-bit scores ($clog2(HASH_BITS+1))
//
// The TIE_BREAK_SENTINEL localparam is a bitmask with all bits set to 1'b1,
// used as the initial / tie-breaking value in the row-priority arbiter.
//==============================================================================
`ifndef CAM_PARAMS_SVH
`define CAM_PARAMS_SVH
// Number of CAM rows.
`ifndef NUM_ROWS
`define NUM_ROWS 4096
`endif
// Width of the hash value stored per row.
`ifndef HASH_BITS
`define HASH_BITS 512
`endif
// Number of parallel comparison lanes.
`ifndef LANES
`define LANES 8
`endif
// Bits required to represent a row index.
`ifndef ROW_BITS
`define ROW_BITS $clog2(`NUM_ROWS)
`endif
// Bits required to represent a full-score count.
`ifndef SCORE_BITS
`define SCORE_BITS $clog2(`HASH_BITS + 1)
`endif
// Tie-break sentinel: all ones in the row-index width.
// Used as the initial best-index value before any match is found.
localparam logic [(`ROW_BITS)-1:0] TIE_BREAK_SENTINEL = {(`ROW_BITS){1'b1}};
// First banked-pipeline implementation requires NUM_ROWS divisible by LANES.
// Tail lanes and unaligned read batches are intentionally out of scope.
`endif // CAM_PARAMS_SVH