Files
Mini-Nav/hw/sim/tests/perf/Makefile
SikongJueluo ca167e79c6 refactor(hw/sim): extract common cocotb make infrastructure into shared mk/ directory
- Split monolithic hw/sim/Makefile into modular include files (mk/cocotb-common.mk, mk/rtl-sources.mk)
- Add per-module test Makefiles (cam_core_banked, cam_read_noise, cam_write_noise, match_engine_pipeline, perf, top)
- Add missing simulation tools (yosys, graphviz, xdot) to devenv.nix
- Fix path handling in sweep_noise.py and test modules to be HASH_BITS-aware
2026-05-16 19:24:17 +08:00

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Makefile

SIM_ROOT := $(abspath ../..)
RTL_ROOT := $(abspath $(SIM_ROOT)/../rtl)
include $(SIM_ROOT)/mk/rtl-sources.mk
TOPLEVEL := cam_top
COCOTB_TEST_MODULES := tests.perf.test_cam_perf
VERILOG_SOURCES := $(RTL_CAM_TOP)
HASH_BITS ?= 512
WRITE_NOISE_EN := 0
READ_NOISE_EN := 0
WRITE_NOISE_BITS := $(shell echo $$(( $(HASH_BITS) / 64 )))
READ_NOISE_BITS := $(shell echo $$(( $(HASH_BITS) / 64 )))
include $(SIM_ROOT)/mk/cocotb-common.mk