SikongJueluo 0fbcd915bd refactor: reorganize RTL files into core/noise subdirectories ...

- Move CAM core modules (cam_core_banked, match_engine_pipeline, popcount_pipeline) to hw/rtl/core/
- Move noise modules (cam_read_noise, cam_write_noise, noise_mask_grouped) to hw/rtl/noise/
- Update Makefile include paths and VERILOG_SOURCES to reflect new layout
- Update docs/experiments.md file path references
- Add sim/results.xml to .gitignore
- Bump devenv.lock dependencies

2026-05-14 20:59:46 +08:00

..

model

feat(hw): add banked CAM pipeline with grouped read/write noise

2026-05-13 18:22:28 +08:00

tests

feat(hw): add banked CAM pipeline with grouped read/write noise

2026-05-13 18:22:28 +08:00

Makefile

refactor: reorganize RTL files into core/noise subdirectories

2026-05-14 20:59:46 +08:00

sweep_noise.py

feat(cam): migrate noise generation from xorshift64 to xorshift128

2026-05-05 20:19:22 +08:00