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https://github.com/SikongJueluo/Mini-Nav.git
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SikongJueluo
f5daaa2667
- Split cam_core into pure memory (cam_core.sv) and match engine (match_engine.sv) - Add cam_params.svh with centralized parameter definitions (NUM_ROWS, HASH_BITS, LANES, etc.) - Update cam_top.sv to use shared parameters and compose match_engine - Update Makefile to include new match_engine module and correct Verilator define syntax
65 lines
1.9 KiB
Systemverilog
65 lines
1.9 KiB
Systemverilog
`timescale 1ns/1ps
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`include "cam_params.svh"
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module cam_top (
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input logic clk,
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input logic rst_n,
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input logic wr_en,
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input logic [(`ROW_BITS)-1:0] wr_row,
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input logic [(`HASH_BITS)-1:0] wr_hash,
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input logic query_valid,
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output logic query_ready,
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input logic [(`HASH_BITS)-1:0] query_hash,
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output logic result_valid,
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input logic result_ready,
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output logic [(`ROW_BITS)-1:0] top1_index,
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output logic [(`SCORE_BITS)-1:0] top1_score,
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`ifdef SIM_NOISE
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input logic [(`LANES)*(`HASH_BITS)-1:0] noise_mask_lanes_flat,
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`endif
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`ifdef SIM_DEBUG
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output logic [(`NUM_ROWS)*(`SCORE_BITS)-1:0] score_debug_flat,
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`endif
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output logic busy
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);
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wire [(`LANES)*(`ROW_BITS)-1:0] rd_addr_lanes_flat;
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wire [(`LANES)*(`HASH_BITS)-1:0] rd_hash_lanes_flat;
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cam_core u_core (
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.clk (clk),
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.rst_n (rst_n),
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.wr_en (wr_en),
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.wr_row (wr_row),
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.wr_hash (wr_hash),
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.rd_addr_lanes_flat (rd_addr_lanes_flat),
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.rd_hash_lanes_flat (rd_hash_lanes_flat)
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);
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match_engine u_match (
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.clk (clk),
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.rst_n (rst_n),
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.query_valid (query_valid),
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.query_ready (query_ready),
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.query_hash (query_hash),
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.result_valid (result_valid),
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.result_ready (result_ready),
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.result_row (top1_index),
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.result_score (top1_score),
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.busy (busy),
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.rd_addr_lanes_flat (rd_addr_lanes_flat),
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.rd_hash_lanes_flat (rd_hash_lanes_flat)
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`ifdef SIM_NOISE
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,.noise_mask_lanes_flat (noise_mask_lanes_flat)
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`endif
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`ifdef SIM_DEBUG
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,.score_debug_flat (score_debug_flat)
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`endif
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);
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endmodule
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