Files
Mini-Nav/hw/syn/Makefile
SikongJueluo 706d148a0b feat(hw): add CAM top-level synthesis infrastructure and fix RTL synthesis compatibility
- Add hw/syn/Makefile with hier/flat/full synth targets and artifact mirroring
- Add synth_cam_top_hier.ys for hierarchy-preserving resource estimation on Xilinx 7-series
- Add synth_cam_top_flat.ys for flattened Xilinx 7-series synthesis
- Add cam-synth just target for convenient invocation
- Guard runtime assertions (NUM_ROWS/LANES checks, noise seed checks, NOISE_BITS checks)
  behind SYNTHESIS guard in cam_core_banked, cam_read_noise, cam_write_noise, and noise_mask_grouped
- Fix shadowed 'return' variable in random128 xorshift128 function
2026-05-18 15:40:04 +08:00

77 lines
3.7 KiB
Makefile

#===============================================================================
# CAM Top Synthesis Makefile
# Targets: synth, hier, flat, clean
# Usage:
# make -C hw/syn synth (defaults, output in build/)
# make -C hw/syn synth OUT_DIR=/some/path (mirror artifacts)
# make -C hw/syn synth NUM_ROWS=8192 (override parameter)
# make -C hw/syn hier (hierarchy-only pass)
# make -C hw/syn flat (flattened-synthesis pass)
# make -C hw/syn clean (remove build/)
#===============================================================================
# ── Configurable variables (defaults) ─────────────────────────────────────────
YOSYS ?= yosys
TOP ?= cam_top
NUM_ROWS ?= 4096
HASH_BITS ?= 512
LANES ?= 8
OUT_DIR ?= build
# ── TOP enforcement (only cam_top is supported) ───────────────────────────────
ifneq ($(TOP),cam_top)
$(error error: only TOP=cam_top is supported)
endif
# ── Internal build directory ──────────────────────────────────────────────────
BUILD_DIR := build
# ── Fixed script and artifact names ───────────────────────────────────────────
HIER_SCRIPT := synth_cam_top_hier.ys
FLAT_SCRIPT := synth_cam_top_flat.ys
HIER_LOG := yosys_hier.log
FLAT_LOG := yosys_flat.log
HIER_JSON := cam_top_hier_resources.json
FLAT_JSON := cam_top_flat_resources.json
SYNTH_V := cam_top_synth.v
ARTIFACTS := $(HIER_JSON) $(FLAT_JSON) $(SYNTH_V) $(HIER_LOG) $(FLAT_LOG)
# ── Yosys command-line defines (always passed) ────────────────────────────────
# cam_params.svh uses `ifndef guards, so -D on the Yosys CLI overrides defaults.
# Use -D NAME=value syntax (Yosys 0.62); do NOT use -define.
YOSYS_DEFINES := -D NUM_ROWS=$(NUM_ROWS) -D HASH_BITS=$(HASH_BITS) -D LANES=$(LANES)
# ── Targets ───────────────────────────────────────────────────────────────────
.PHONY: synth hier flat clean
# ── Hierarchy resource reference pass ─────────────────────────────────────────
hier:
mkdir -p $(BUILD_DIR)
$(YOSYS) $(YOSYS_DEFINES) -l $(BUILD_DIR)/$(HIER_LOG) -s $(HIER_SCRIPT)
# ── Flattened Xilinx synthesis pass ───────────────────────────────────────────
flat:
mkdir -p $(BUILD_DIR)
$(YOSYS) $(YOSYS_DEFINES) -l $(BUILD_DIR)/$(FLAT_LOG) -s $(FLAT_SCRIPT)
# ── Full synthesis: hier + flat, then mirror artifacts to OUT_DIR if different ─
synth: hier flat
@if [ "$(abspath $(OUT_DIR))" != "$(abspath $(BUILD_DIR))" ]; then \
set -e; \
echo "Mirroring artifacts to $(OUT_DIR) ..."; \
mkdir -p "$(OUT_DIR)"; \
for f in $(ARTIFACTS); do \
if [ ! -f "$(BUILD_DIR)/$$f" ]; then \
echo "error: missing artifact $(BUILD_DIR)/$$f" >&2; \
exit 1; \
fi; \
cp "$(BUILD_DIR)/$$f" "$(OUT_DIR)/$$f"; \
done; \
fi
# ── Clean ─────────────────────────────────────────────────────────────────────
clean:
rm -rf $(BUILD_DIR)