mirror of
https://github.com/SikongJueluo/Mini-Nav.git
synced 2026-07-12 20:15:31 +08:00
SikongJueluo
8f59a287c4
- Add cam_core_banked.sv with 8-lane banked CAM core - Add cam_write_noise.sv and cam_read_noise.sv for grouped noise injection - Add noise_mask_grouped.sv generating grouped flip masks from 128-bit PRNG - Add match_engine_pipeline.sv with multi-stage pipelined top-1 selection - Add popcount_pipeline.sv for pipelined popcount operations - Refactor test_cam_basic.py with parametrized DUT introspection helpers - Add Python ref_model match_top1_with_read_noise() for read noise verification - Update Makefile with separate WRITE_NOISE_* and READ_NOISE_* parameter groups - Add new testbenches: test_cam_core_banked, test_cam_read_noise, test_cam_write_noise, test_match_engine_pipeline, test_ref_model_noise breaking change hint: NUM_ROWS default changed from 512→4096, LANES from 16→8
58 lines
2.0 KiB
Systemverilog
58 lines
2.0 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "cam_params.svh"
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module cam_core_banked (
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input logic clk,
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input logic rst_n,
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input logic wr_valid,
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output logic wr_ready,
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input logic [(`ROW_BITS)-1:0] wr_row,
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input logic [(`HASH_BITS)-1:0] wr_hash,
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input logic rd_valid_i,
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input logic [(`ROW_BITS)-1:0] rd_base_row_i,
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output logic rd_valid_o,
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output logic [(`LANES)*(`ROW_BITS)-1:0] rd_row_ids_o,
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output logic [(`LANES)*(`HASH_BITS)-1:0] rd_hashes_o,
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output logic [(`LANES)-1:0] rd_lane_valid_o
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);
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localparam int BANKS = `LANES;
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localparam int BANK_DEPTH = `NUM_ROWS / `LANES;
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(* ram_style = "block" *) logic [(`HASH_BITS)-1:0] bank_mem [0:BANKS-1][0:BANK_DEPTH-1];
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assign wr_ready = 1'b1;
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initial begin
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if (`NUM_ROWS % `LANES != 0) $fatal(1, "NUM_ROWS must be divisible by LANES");
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end
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always_ff @(posedge clk) begin
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if (wr_valid) begin
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bank_mem[wr_row % `LANES][wr_row / `LANES] <= wr_hash;
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end
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end
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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rd_valid_o <= 1'b0;
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rd_row_ids_o <= '0;
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rd_hashes_o <= '0;
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rd_lane_valid_o <= '0;
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end else begin
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rd_valid_o <= rd_valid_i;
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rd_lane_valid_o <= rd_valid_i ? {`LANES{1'b1}} : '0;
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if (rd_valid_i && ((rd_base_row_i % `LANES) != 0)) begin
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$fatal(1, "rd_base_row_i must be LANES-aligned");
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end
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for (int lane = 0; lane < `LANES; lane++) begin
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rd_row_ids_o[lane*`ROW_BITS +: `ROW_BITS] <= rd_base_row_i + lane[(`ROW_BITS)-1:0];
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rd_hashes_o[lane*`HASH_BITS +: `HASH_BITS] <= bank_mem[lane][rd_base_row_i / `LANES];
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end
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end
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end
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endmodule
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