mirror of
https://github.com/SikongJueluo/Mini-Nav.git
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SikongJueluo
706d148a0b
- Add hw/syn/Makefile with hier/flat/full synth targets and artifact mirroring - Add synth_cam_top_hier.ys for hierarchy-preserving resource estimation on Xilinx 7-series - Add synth_cam_top_flat.ys for flattened Xilinx 7-series synthesis - Add cam-synth just target for convenient invocation - Guard runtime assertions (NUM_ROWS/LANES checks, noise seed checks, NOISE_BITS checks) behind SYNTHESIS guard in cam_core_banked, cam_read_noise, cam_write_noise, and noise_mask_grouped - Fix shadowed 'return' variable in random128 xorshift128 function
88 lines
3.3 KiB
Systemverilog
88 lines
3.3 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "cam_params.svh"
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module cam_read_noise #(
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parameter bit READ_NOISE_EN = 1'b1,
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parameter int READ_NOISE_RATE_NUM = 1,
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parameter int READ_NOISE_RATE_DEN = 100,
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parameter int READ_NOISE_BITS = 8,
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parameter logic [63:0] READ_NOISE_SEED = 64'h6A09_E667_F3BC_C909
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) (
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input logic clk,
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input logic rst_n,
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input logic valid_i,
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input logic [(`LANES)*(`ROW_BITS)-1:0] row_ids_i,
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input logic [(`LANES)*(`HASH_BITS)-1:0] hashes_i,
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input logic [(`LANES)-1:0] lane_valid_i,
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output logic valid_o,
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output logic [(`LANES)*(`ROW_BITS)-1:0] row_ids_o,
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output logic [(`LANES)*(`HASH_BITS)-1:0] hashes_noisy_o,
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output logic [(`LANES)-1:0] lane_valid_o
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);
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logic valid_q;
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logic [(`LANES)*(`ROW_BITS)-1:0] row_ids_q;
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logic [(`LANES)*(`HASH_BITS)-1:0] hashes_q;
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logic [(`LANES)-1:0] lane_valid_q;
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logic [127:0] random_num [0:`LANES-1];
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logic [(`HASH_BITS)-1:0] mask [0:`LANES-1];
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`ifndef SYNTHESIS
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initial begin
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if (READ_NOISE_SEED == 64'd0) $fatal(1, "READ_NOISE_SEED must be nonzero");
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end
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`endif
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generate
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for (genvar lane = 0; lane < `LANES; lane++) begin : gen_lane_noise
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localparam logic [63:0] LANE_SALT = 64'(lane + 1) * 64'h9E37_79B9_7F4A_7C15;
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random128 u_random_read (
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.clk (clk),
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.rst_n (rst_n),
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.enable(valid_i && lane_valid_i[lane] && READ_NOISE_EN && (READ_NOISE_RATE_NUM > 0)),
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.seed ({(READ_NOISE_SEED ^ LANE_SALT), (READ_NOISE_SEED ^ LANE_SALT)}),
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.out (random_num[lane])
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);
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noise_mask_grouped #(
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.HASH_BITS (`HASH_BITS),
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.NOISE_BITS (READ_NOISE_BITS),
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.NOISE_RATE_NUM (READ_NOISE_RATE_NUM),
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.NOISE_RATE_DEN (READ_NOISE_RATE_DEN)
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) u_mask (
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.random_i(random_num[lane]),
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.mask_o (mask[lane])
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);
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end
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endgenerate
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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valid_q <= 1'b0;
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row_ids_q <= '0;
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hashes_q <= '0;
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lane_valid_q <= '0;
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valid_o <= 1'b0;
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row_ids_o <= '0;
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hashes_noisy_o <= '0;
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lane_valid_o <= '0;
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end else begin
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valid_q <= valid_i;
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row_ids_q <= row_ids_i;
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hashes_q <= hashes_i;
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lane_valid_q <= lane_valid_i;
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valid_o <= valid_q;
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row_ids_o <= row_ids_q;
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lane_valid_o <= lane_valid_q;
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for (int lane = 0; lane < `LANES; lane++) begin
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if (READ_NOISE_EN && (READ_NOISE_RATE_NUM > 0) && lane_valid_q[lane]) begin
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hashes_noisy_o[lane*`HASH_BITS +: `HASH_BITS] <= hashes_q[lane*`HASH_BITS +: `HASH_BITS] ^ mask[lane];
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end else begin
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hashes_noisy_o[lane*`HASH_BITS +: `HASH_BITS] <= hashes_q[lane*`HASH_BITS +: `HASH_BITS];
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end
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end
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end
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end
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endmodule
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