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SikongJueluo
f5daaa2667
- Split cam_core into pure memory (cam_core.sv) and match engine (match_engine.sv) - Add cam_params.svh with centralized parameter definitions (NUM_ROWS, HASH_BITS, LANES, etc.) - Update cam_top.sv to use shared parameters and compose match_engine - Update Makefile to include new match_engine module and correct Verilator define syntax
33 lines
981 B
Systemverilog
33 lines
981 B
Systemverilog
`timescale 1ns / 1ps
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`include "cam_params.svh"
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module cam_core (
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input logic clk,
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input logic rst_n,
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input logic wr_en,
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input logic [(`ROW_BITS)-1:0] wr_row,
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input logic [(`HASH_BITS)-1:0] wr_hash,
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input logic [(`LANES)*(`ROW_BITS)-1:0] rd_addr_lanes_flat,
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output logic [(`LANES)*(`HASH_BITS)-1:0] rd_hash_lanes_flat
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);
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logic [(`HASH_BITS)-1:0] cam_mem[0:(`NUM_ROWS)-1];
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// Memory write path.
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always_ff @(posedge clk) begin
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if (wr_en) begin
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cam_mem[wr_row] <= wr_hash;
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end
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end
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// Per-lane combinational read.
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genvar l;
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generate
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for (l = 0; l < `LANES; l++) begin : rd_lane
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assign rd_hash_lanes_flat[l*`HASH_BITS +: `HASH_BITS] =
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cam_mem[rd_addr_lanes_flat[l*`ROW_BITS +: `ROW_BITS]];
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end
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endgenerate
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endmodule
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