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https://github.com/SikongJueluo/Mini-Nav.git
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SikongJueluo
8b4d4c1b57
- Make cam_read_noise a pass-through module, removing all noise injection logic - Switch write noise to use noise_mask_bernoulli instead of noise_mask_grouped - Add state machine to cam_write_noise for mask generation timing - Remove noise_mask_grouped.sv (no longer needed) - Remove read noise parameters from cam_noisy and cam_top - Update simulation and benchmark code to reflect read noise removal - Sync documentation to reflect Phase 2 architecture
114 lines
3.7 KiB
Systemverilog
114 lines
3.7 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "cam_params.svh"
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module cam_write_noise #(
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parameter bit WRITE_NOISE_EN = 1'b1,
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parameter int WRITE_NOISE_RATE_NUM = 1,
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parameter int WRITE_NOISE_RATE_DEN = 100,
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parameter logic [63:0] WRITE_NOISE_SEED = 64'hB504_F32D_B504_F32D
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) (
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input logic clk,
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input logic rst_n,
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input logic wr_valid,
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output logic wr_ready,
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input logic [(`ROW_BITS)-1:0] wr_row,
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input logic [(`HASH_BITS)-1:0] wr_hash,
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output logic core_wr_valid,
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output logic [(`ROW_BITS)-1:0] core_wr_row,
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output logic [(`HASH_BITS)-1:0] core_wr_hash
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);
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localparam int PROB_BITS = 8;
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localparam int SAMPLE_RANGE = 1 << PROB_BITS;
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localparam int WRITE_NOISE_THRESHOLD_RAW =
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(WRITE_NOISE_RATE_NUM * SAMPLE_RANGE) / WRITE_NOISE_RATE_DEN;
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localparam int WRITE_NOISE_THRESHOLD =
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(WRITE_NOISE_THRESHOLD_RAW > (SAMPLE_RANGE - 1)) ?
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(SAMPLE_RANGE - 1) : WRITE_NOISE_THRESHOLD_RAW;
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wire noise_active = WRITE_NOISE_EN && (WRITE_NOISE_RATE_NUM > 0) && (WRITE_NOISE_THRESHOLD > 0);
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typedef enum logic [1:0] {
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STATE_IDLE,
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STATE_WAIT_MASK
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} state_t;
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state_t state_q;
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logic mask_start_q;
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logic mask_busy;
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logic mask_done;
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logic [(`HASH_BITS)-1:0] flip_mask;
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logic [(`ROW_BITS)-1:0] row_q;
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logic [(`HASH_BITS)-1:0] hash_q;
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assign wr_ready = (state_q == STATE_IDLE);
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noise_mask_bernoulli #(
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.HASH_BITS (`HASH_BITS),
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.PROB_BITS (PROB_BITS),
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.PRNG_WORDS (2),
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.BITS_PER_CYCLE (32),
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.SEED (WRITE_NOISE_SEED)
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) u_bernoulli_mask (
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.clk (clk),
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.rst_n (rst_n),
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.start_i (mask_start_q),
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.threshold_i (PROB_BITS'(WRITE_NOISE_THRESHOLD)),
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.busy_o (mask_busy),
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.done_o (mask_done),
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.mask_o (flip_mask)
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);
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`ifndef SYNTHESIS
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initial begin
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if (WRITE_NOISE_SEED == 64'd0) $fatal(1, "WRITE_NOISE_SEED must be nonzero");
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end
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`endif
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state_q <= STATE_IDLE;
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mask_start_q <= 1'b0;
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row_q <= '0;
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hash_q <= '0;
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core_wr_valid <= 1'b0;
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core_wr_row <= '0;
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core_wr_hash <= '0;
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end else begin
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core_wr_valid <= 1'b0;
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mask_start_q <= 1'b0;
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unique case (state_q)
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STATE_IDLE: begin
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if (wr_valid && wr_ready) begin
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row_q <= wr_row;
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hash_q <= wr_hash;
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if (noise_active) begin
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mask_start_q <= 1'b1;
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state_q <= STATE_WAIT_MASK;
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end else begin
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// Noise inactive: pass through immediately (one-cycle)
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core_wr_valid <= 1'b1;
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core_wr_row <= wr_row;
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core_wr_hash <= wr_hash;
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end
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end
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end
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STATE_WAIT_MASK: begin
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if (mask_done) begin
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core_wr_valid <= 1'b1;
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core_wr_row <= row_q;
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core_wr_hash <= hash_q ^ flip_mask;
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state_q <= STATE_IDLE;
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end
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end
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default: begin
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state_q <= STATE_IDLE;
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end
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endcase
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end
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end
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endmodule
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