mirror of
https://github.com/SikongJueluo/Mini-Nav.git
synced 2026-07-12 20:15:31 +08:00
SikongJueluo
e4cbb5e30d
- add TOPK_K, FIFO_DEPTH, RESULT_SERIAL parameters to cam_params - add candidate_fifo: synchronous ready/valid FIFO for (row, score) candidates - add topk_tracker: tracks top-K candidates with clear/ready handshake - add result_serializer: serializes packed Top-K array into rank-ordered stream - refactor match_engine_pipeline from 4-state to 8-state Top-K pipeline - extend cam_top with serial Top-K interface (result_rank/row/score/last) - add backward-compatible top1_index/top1_score aliases from rank-0 beat - add comprehensive tests for all new modules
125 lines
5.0 KiB
Systemverilog
125 lines
5.0 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "cam_params.svh"
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//==============================================================================
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// candidate_fifo — Synchronous ready/valid FIFO for (row, score) candidates
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//
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// Implements a simple circular-buffer FIFO that accepts writes only when
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// wr_valid_i && wr_ready_o and reads only when rd_valid_o && rd_ready_i.
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// Provides empty/full flags. Default depth is `FIFO_DEPTH (16).
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//
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// Quality:
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// - Pointers always wrap at DEPTH-1 (safe for non-power-of-two depths).
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// - wr_ready_o goes high when full if a read is accepted in the same cycle,
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// allowing a simultaneous write (throughput-friendly backpressure).
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// - PTR_BITS is at least 1 for DEPTH=1.
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//==============================================================================
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module candidate_fifo #(
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parameter int DEPTH = `FIFO_DEPTH,
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parameter int ROW_BITS = `ROW_BITS,
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parameter int SCORE_BITS = `SCORE_BITS,
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// Ensure at least 1 bit even when DEPTH=1.
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parameter int PTR_BITS = (DEPTH <= 1) ? 1 : $clog2(DEPTH)
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) (
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input logic clk,
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input logic rst_n,
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// Write interface (producer side)
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input logic wr_valid_i,
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output logic wr_ready_o,
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input logic [ROW_BITS -1:0] wr_row_i,
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input logic [SCORE_BITS -1:0] wr_score_i,
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// Read interface (consumer side)
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output logic rd_valid_o,
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input logic rd_ready_i,
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output logic [ROW_BITS -1:0] rd_row_o,
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output logic [SCORE_BITS -1:0] rd_score_o,
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// Status flags
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output logic empty_o,
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output logic full_o
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);
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//--------------------------------------------------------------------------
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// Storage — dual‑port array.
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//--------------------------------------------------------------------------
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logic [ROW_BITS -1:0] mem_row [0:DEPTH-1];
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logic [SCORE_BITS -1:0] mem_score [0:DEPTH-1];
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//--------------------------------------------------------------------------
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// Pointers and fill counter
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//--------------------------------------------------------------------------
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logic [PTR_BITS -1:0] wr_ptr, rd_ptr;
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logic [PTR_BITS :0] count; // extra bit for full detect
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// Wrap-at value (DEPTH-1), sized to match pointer width.
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// Part-select DEPTH and use a 1'b1 literal so the RHS width equals PTR_BITS.
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localparam logic [PTR_BITS-1:0] WRAP_AT = DEPTH[PTR_BITS-1:0] - 1'b1;
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//--------------------------------------------------------------------------
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// Status flag outputs (combinational)
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//--------------------------------------------------------------------------
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assign empty_o = (count == 0);
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assign full_o = (count == DEPTH[PTR_BITS:0]);
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//--------------------------------------------------------------------------
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// Handshake outputs
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//
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// wr_ready_o is asserted when not full, OR when a read is accepted in
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// the same cycle (full+pop → slot freed → write can proceed).
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//--------------------------------------------------------------------------
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assign wr_ready_o = ~full_o | (rd_valid_o & rd_ready_i);
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assign rd_valid_o = ~empty_o;
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//--------------------------------------------------------------------------
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// Read data (combinational — value at current rd_ptr)
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//--------------------------------------------------------------------------
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assign rd_row_o = mem_row [rd_ptr];
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assign rd_score_o = mem_score[rd_ptr];
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//--------------------------------------------------------------------------
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// Push / Pop decode
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//--------------------------------------------------------------------------
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logic push, pop;
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assign push = wr_valid_i & wr_ready_o;
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assign pop = rd_valid_o & rd_ready_i;
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//--------------------------------------------------------------------------
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// Sequential — pointer and count updates
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//
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// Pointers wrap at DEPTH-1, safe for any DEPTH (not just powers of two).
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// Simultaneous push+pop leaves count unchanged.
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//--------------------------------------------------------------------------
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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wr_ptr <= 0;
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rd_ptr <= 0;
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count <= 0;
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end else begin
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if (push) begin
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mem_row [wr_ptr] <= wr_row_i;
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mem_score[wr_ptr] <= wr_score_i;
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if (wr_ptr == WRAP_AT)
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wr_ptr <= 0;
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else
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wr_ptr <= wr_ptr + 1;
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end
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if (pop) begin
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if (rd_ptr == WRAP_AT)
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rd_ptr <= 0;
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else
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rd_ptr <= rd_ptr + 1;
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end
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// Update fill count
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if (push & ~pop) count <= count + 1;
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else if (~push & pop) count <= count - 1;
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// else: no change (neither, or both)
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end
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end
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endmodule
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