`timescale 1ns/1ps
`include "cam_params.svh"

module cam_top (
    input  logic clk,
    input  logic rst_n,

    input  logic                  wr_en,
    input  logic [(`ROW_BITS)-1:0]   wr_row,
    input  logic [(`HASH_BITS)-1:0]  wr_hash,

    input  logic                  query_valid,
    output logic                  query_ready,
    input  logic [(`HASH_BITS)-1:0]  query_hash,

    output logic                  result_valid,
    input  logic                  result_ready,
    output logic [(`ROW_BITS)-1:0]   top1_index,
    output logic [(`SCORE_BITS)-1:0] top1_score,

`ifdef SIM_NOISE
    input  logic [(`LANES)*(`HASH_BITS)-1:0] noise_mask_lanes_flat,
`endif

`ifdef SIM_DEBUG
    output logic [(`NUM_ROWS)*(`SCORE_BITS)-1:0] score_debug_flat,
`endif

    output logic busy
);
    wire [(`LANES)*(`ROW_BITS)-1:0]  rd_addr_lanes_flat;
    wire [(`LANES)*(`HASH_BITS)-1:0] rd_hash_lanes_flat;

    cam_core u_core (
        .clk                (clk),
        .rst_n              (rst_n),
        .wr_en              (wr_en),
        .wr_row             (wr_row),
        .wr_hash            (wr_hash),
        .rd_addr_lanes_flat (rd_addr_lanes_flat),
        .rd_hash_lanes_flat (rd_hash_lanes_flat)
    );

    match_engine u_match (
        .clk                (clk),
        .rst_n              (rst_n),
        .query_valid        (query_valid),
        .query_ready        (query_ready),
        .query_hash         (query_hash),
        .result_valid       (result_valid),
        .result_ready       (result_ready),
        .result_row         (top1_index),
        .result_score       (top1_score),
        .busy               (busy),
        .rd_addr_lanes_flat (rd_addr_lanes_flat),
        .rd_hash_lanes_flat (rd_hash_lanes_flat)
`ifdef SIM_NOISE
        ,.noise_mask_lanes_flat (noise_mask_lanes_flat)
`endif
`ifdef SIM_DEBUG
        ,.score_debug_flat (score_debug_flat)
`endif
    );
endmodule