`timescale 1ns / 1ps
`include "cam_params.svh"

module cam_core (
    input  logic                                clk,
    input  logic                                rst_n,
    input  logic                                wr_en,
    input  logic [(`ROW_BITS)-1:0]              wr_row,
    input  logic [(`HASH_BITS)-1:0]             wr_hash,
    input  logic [(`LANES)*(`ROW_BITS)-1:0]     rd_addr_lanes_flat,
    output logic [(`LANES)*(`HASH_BITS)-1:0]    rd_hash_lanes_flat
);

    logic [(`HASH_BITS)-1:0] cam_mem[0:(`NUM_ROWS)-1];

    // Memory write path.
    always_ff @(posedge clk) begin
        if (wr_en) begin
            cam_mem[wr_row] <= wr_hash;
        end
    end

    // Per-lane combinational read.
    genvar l;
    generate
        for (l = 0; l < `LANES; l++) begin : rd_lane
            assign rd_hash_lanes_flat[l*`HASH_BITS +: `HASH_BITS] =
                   cam_mem[rd_addr_lanes_flat[l*`ROW_BITS +: `ROW_BITS]];
        end
    endgenerate

endmodule