`timescale 1ns / 1ps
`include "cam_params.svh"

// Design constraints:
//   HASH_BITS % NOISE_BITS == 0
//   GROUP_BITS (= HASH_BITS / NOISE_BITS) == 64 (needed for 6-bit index)
//   NOISE_BITS * GROUP_RAND_BITS <= 128
//   0 <= NOISE_RATE_NUM <= NOISE_RATE_DEN
//   NOISE_RATE_DEN > 0
//   NOISE_SEED != 64'd0
//   NOISE_BITS > 0

module cam_noisy #(
    parameter bit          NOISE_EN          = 1'b1,
    parameter int          NOISE_RATE_NUM    = 70,
    parameter int          NOISE_RATE_DEN    = 100,
    parameter logic [63:0] NOISE_SEED        = 64'hB504_F32D_B504_F32D,
    parameter int          NOISE_BITS        = 8
) (
    input logic clk,
    input logic rst_n,

    // Write interface (handshake)
    input  logic                    wr_valid,
    output logic                    wr_ready,
    input  logic [ (`ROW_BITS)-1:0] wr_addr,
    input  logic [(`HASH_BITS)-1:0] write_hash,

    // Read interface (passthrough to cam_core, combinational read)
    input  logic [ (`LANES)*(`ROW_BITS)-1:0] rd_addr_lanes_flat,
    output logic [(`LANES)*(`HASH_BITS)-1:0] rd_hash_lanes_flat
);

    // ── Local parameters ──
    localparam int GROUP_BITS       = `HASH_BITS / NOISE_BITS;
    localparam int BIT_INDEX_BITS   = 6;
    localparam int SAMPLE_BITS      = 8;
    localparam int GROUP_RAND_BITS  = BIT_INDEX_BITS + SAMPLE_BITS;  // 14
    localparam int SAMPLE_RANGE     = 2 ** SAMPLE_BITS;              // 256
    localparam int THRESHOLD        = (NOISE_RATE_NUM * SAMPLE_RANGE) / NOISE_RATE_DEN;

    // ── Elaboration-time parameter checks ──
    initial begin
        if (NOISE_BITS <= 0)
            $fatal(1, "NOISE_BITS must be > 0, got %0d", NOISE_BITS);
        if (`HASH_BITS % NOISE_BITS != 0)
            $fatal(1, "HASH_BITS (%0d) must be divisible by NOISE_BITS (%0d)", `HASH_BITS, NOISE_BITS);
        if (GROUP_BITS != 64)
            $fatal(1, "GROUP_BITS (= HASH_BITS/NOISE_BITS) must equal 64 for 6-bit index, got %0d", GROUP_BITS);
        if (NOISE_BITS * GROUP_RAND_BITS > 128)
            $fatal(1, "NOISE_BITS*GROUP_RAND_BITS must be <= 128, got %0d", NOISE_BITS * GROUP_RAND_BITS);
        if (NOISE_RATE_DEN <= 0)
            $fatal(1, "NOISE_RATE_DEN must be > 0, got %0d", NOISE_RATE_DEN);
        if (NOISE_RATE_NUM < 0 || NOISE_RATE_NUM > NOISE_RATE_DEN)
            $fatal(1, "NOISE_RATE_NUM (%0d) must be in [0, NOISE_RATE_DEN=%0d]", NOISE_RATE_NUM, NOISE_RATE_DEN);
        if (NOISE_SEED == 64'd0)
            $fatal(1, "NOISE_SEED must be nonzero — xorshift128/random128 with zero seed never advances");
    end

    // ── FSM states ──
    typedef enum logic [1:0] {
        S_IDLE,
        S_GEN_MASK,
        S_COMMIT
    } state_t;

    state_t curr_state, next_state;

    // ── Latch registers ──
    logic [(`ROW_BITS)-1:0]  addr_q;
    logic [(`HASH_BITS)-1:0] write_hash_q;

    // ── Noise generation ──
    logic [(`HASH_BITS)-1:0] flip_mask;
    logic [127:0]            random_num;

    // ── Combinational next-mask helper ──
    // Computes flip_mask_next from fresh random_num in one cycle.
    logic [(`HASH_BITS)-1:0] flip_mask_next;
    always_comb begin
        flip_mask_next = '0;
        for (int i = 0; i < NOISE_BITS; i++) begin
            if (random_num[i * GROUP_RAND_BITS + BIT_INDEX_BITS +: SAMPLE_BITS] < THRESHOLD) begin
                flip_mask_next[i * GROUP_BITS + random_num[i * GROUP_RAND_BITS +: BIT_INDEX_BITS]] = 1'b1;
            end
        end
    end

    // ── Noisy hash for cam_core write ──
    logic [(`HASH_BITS)-1:0] noisy_hash;
    assign noisy_hash = write_hash_q ^ flip_mask;

    // ── wr_ready: only in IDLE ──
    assign wr_ready = (curr_state == S_IDLE);

    // ── random128 enable: advance random on accepted noisy write ──
    logic random_enable;
    assign random_enable = wr_ready && wr_valid && NOISE_EN && (NOISE_RATE_NUM > 0);

    // ── FSM block 1: state register ──
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            curr_state <= S_IDLE;
        end else begin
            curr_state <= next_state;
        end
    end

    // ── FSM block 2: next-state logic ──
    always_comb begin
        next_state = curr_state;
        case (curr_state)
            S_IDLE: begin
                if (wr_valid && wr_ready) begin
                    if (NOISE_EN && (NOISE_RATE_NUM > 0)) next_state = S_GEN_MASK;
                    else next_state = S_COMMIT;
                end
            end

            S_GEN_MASK: begin
                next_state = S_COMMIT;
            end

            S_COMMIT: begin
                next_state = S_IDLE;
            end

            default: next_state = S_IDLE;
        endcase
    end

    // ── FSM block 3: state actions / datapath registers ──
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            addr_q       <= '0;
            write_hash_q <= '0;
            flip_mask    <= '0;
        end else begin
            case (curr_state)
                S_IDLE: begin
                    flip_mask <= '0;
                    if (wr_valid && wr_ready) begin
                        addr_q       <= wr_addr;
                        write_hash_q <= write_hash;
                    end
                end

                S_GEN_MASK: begin
                    flip_mask <= flip_mask_next;
                end

                S_COMMIT: begin
                    // Write happens via combinational core_wr_en
                end

                default: ;  // No-op
            endcase
        end
    end

    // ── cam_core instance ──
    logic                    core_wr_en;
    logic [ (`ROW_BITS)-1:0] core_wr_row;
    logic [(`HASH_BITS)-1:0] core_wr_hash;

    assign core_wr_en   = (curr_state == S_COMMIT);
    assign core_wr_row  = addr_q;
    assign core_wr_hash = noisy_hash;

    cam_core u_core (
        .clk               (clk),
        .rst_n             (rst_n),
        .wr_en             (core_wr_en),
        .wr_row            (core_wr_row),
        .wr_hash           (core_wr_hash),
        .rd_addr_lanes_flat(rd_addr_lanes_flat),
        .rd_hash_lanes_flat(rd_hash_lanes_flat)
    );

    // ── Random number generator ──
    random128 u_random_128 (
        .clk   (clk),
        .rst_n (rst_n),
        .enable(random_enable),
        .seed  ({NOISE_SEED, NOISE_SEED}),
        .out   (random_num)
    );

endmodule