`timescale 1ns / 1ps

module random64 (
    input  logic        clk,
    input  logic        rst_n,
    input  logic        enable,
    input  logic [63:0] seed,
    output logic [63:0] out
);

    function automatic logic [63:0] xorshift64(input logic [63:0] x);
        logic [63:0] s;
        s = x;
        s ^= s << 13;
        s ^= s >> 7;
        s ^= s << 17;
        return s;
    endfunction

    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            out <= seed;
        end else if (enable) begin
            out <= xorshift64(out);
        end
    end

endmodule