SIM ?= verilator TOPLEVEL_LANG ?= verilog TOPLEVEL ?= cam_top COCOTB_TEST_MODULES ?= tests.test_cam_basic NUM_ROWS ?= 4096 HASH_BITS ?= 512 LANES ?= 8 EXTRA_ARGS += +define+NUM_ROWS=$(NUM_ROWS) +define+HASH_BITS=$(HASH_BITS) +define+LANES=$(LANES) COMPILE_ARGS += -Wall -Wno-fatal COMPILE_ARGS += -I$(PWD)/../rtl COMPILE_ARGS += +define+SIM_DEBUG COMPILE_ARGS += $(EXTRA_DEFINES) # Noise parameters — only passed when explicitly set (non-empty). # For cam_noisy/cam_top tests, pass WRITE_NOISE_*=... READ_NOISE_*=... # For individual module tests, leave them unset to skip. WRITE_NOISE_EN ?= $(NOISE_EN) WRITE_NOISE_RATE_NUM ?= $(NOISE_RATE_NUM) WRITE_NOISE_RATE_DEN ?= $(NOISE_RATE_DEN) WRITE_NOISE_BITS ?= $(NOISE_BITS) READ_NOISE_EN ?= READ_NOISE_RATE_NUM ?= READ_NOISE_RATE_DEN ?= READ_NOISE_BITS ?= ifneq ($(strip $(WRITE_NOISE_EN)),) COMPILE_ARGS += -GWRITE_NOISE_EN=$(WRITE_NOISE_EN) endif ifneq ($(strip $(WRITE_NOISE_RATE_NUM)),) COMPILE_ARGS += -GWRITE_NOISE_RATE_NUM=$(WRITE_NOISE_RATE_NUM) endif ifneq ($(strip $(WRITE_NOISE_RATE_DEN)),) COMPILE_ARGS += -GWRITE_NOISE_RATE_DEN=$(WRITE_NOISE_RATE_DEN) endif ifneq ($(strip $(WRITE_NOISE_BITS)),) COMPILE_ARGS += -GWRITE_NOISE_BITS=$(WRITE_NOISE_BITS) endif ifneq ($(strip $(READ_NOISE_EN)),) COMPILE_ARGS += -GREAD_NOISE_EN=$(READ_NOISE_EN) endif ifneq ($(strip $(READ_NOISE_RATE_NUM)),) COMPILE_ARGS += -GREAD_NOISE_RATE_NUM=$(READ_NOISE_RATE_NUM) endif ifneq ($(strip $(READ_NOISE_RATE_DEN)),) COMPILE_ARGS += -GREAD_NOISE_RATE_DEN=$(READ_NOISE_RATE_DEN) endif ifneq ($(strip $(READ_NOISE_BITS)),) COMPILE_ARGS += -GREAD_NOISE_BITS=$(READ_NOISE_BITS) endif # Cleaner terminal output export QUIET ?= 1 export VERBOSE ?= 0 export COCOTB_LOG_LEVEL ?= INFO export PYTHONWARNINGS ?= ignore::pytest.PytestDeprecationWarning # Optional temporary suppression SUPPRESS_VERILATOR_WARNINGS ?= 0 ifeq ($(SUPPRESS_VERILATOR_WARNINGS),1) COMPILE_ARGS += -Wno-WIDTHEXPAND COMPILE_ARGS += -Wno-UNOPTFLAT endif VERILOG_SOURCES += $(PWD)/../rtl/popcount.sv VERILOG_SOURCES += $(PWD)/../rtl/argmax_update.sv VERILOG_SOURCES += $(PWD)/../rtl/cam_core.sv VERILOG_SOURCES += $(PWD)/../rtl/random/random128.sv VERILOG_SOURCES += $(PWD)/../rtl/noise_mask_grouped.sv VERILOG_SOURCES += $(PWD)/../rtl/cam_core_banked.sv VERILOG_SOURCES += $(PWD)/../rtl/cam_write_noise.sv VERILOG_SOURCES += $(PWD)/../rtl/cam_read_noise.sv VERILOG_SOURCES += $(PWD)/../rtl/popcount_pipeline.sv VERILOG_SOURCES += $(PWD)/../rtl/match_engine_pipeline.sv VERILOG_SOURCES += $(PWD)/../rtl/cam_noisy.sv VERILOG_SOURCES += $(PWD)/../rtl/match_engine.sv VERILOG_SOURCES += $(PWD)/../rtl/cam_top.sv include $(shell uv run cocotb-config --makefiles)/Makefile.sim