SIM_ROOT := $(abspath ../../..)
RTL_ROOT := $(abspath $(SIM_ROOT)/../rtl)
include $(SIM_ROOT)/mk/rtl-sources.mk

TOPLEVEL := popcount_pipeline
COCOTB_TEST_MODULES := tests.modules.popcount_pipeline.test_popcount_pipeline
VERILOG_SOURCES := $(RTL_MATCH_ENGINE)

include $(SIM_ROOT)/mk/cocotb-common.mk