`timescale 1ns / 1ps
`include "cam_params.svh"

module cam_read_noise (
    input  logic                              clk,
    input  logic                              rst_n,
    input  logic                              valid_i,
    input  logic [(`LANES)*(`ROW_BITS)-1:0]   row_ids_i,
    input  logic [(`LANES)*(`HASH_BITS)-1:0]  hashes_i,
    input  logic [(`LANES)-1:0]               lane_valid_i,
    output logic                              valid_o,
    output logic [(`LANES)*(`ROW_BITS)-1:0]   row_ids_o,
    output logic [(`LANES)*(`HASH_BITS)-1:0]  hashes_noisy_o,
    output logic [(`LANES)-1:0]               lane_valid_o
);

    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            valid_o        <= 1'b0;
            row_ids_o      <= '0;
            hashes_noisy_o <= '0;
            lane_valid_o   <= '0;
        end else begin
            valid_o        <= valid_i;
            row_ids_o      <= row_ids_i;
            hashes_noisy_o <= hashes_i;
            lane_valid_o   <= lane_valid_i;
        end
    end

endmodule