# synth_cam_top_flat.ys — Flattened CAM top synthesis for Xilinx Zynq-7020 / 7-series
# Run from hw/syn: yosys -s synth_cam_top_flat.ys

# Set include directories before reading RTL
verilog_defaults -push
verilog_defaults -add -I../rtl
verilog_defaults -add -I../rtl/core
verilog_defaults -add -I../rtl/noise
verilog_defaults -add -I../rtl/random

# Read RTL sources in canonical order
read_verilog -sv -D SYNTHESIS ../rtl/random/random128.sv
read_verilog -sv -D SYNTHESIS ../rtl/noise/noise_mask_grouped.sv
read_verilog -sv -D SYNTHESIS ../rtl/noise/cam_write_noise.sv
read_verilog -sv -D SYNTHESIS ../rtl/noise/cam_read_noise.sv
read_verilog -sv -D SYNTHESIS ../rtl/core/cam_core_banked.sv
read_verilog -sv -D SYNTHESIS ../rtl/core/popcount_pipeline.sv
read_verilog -sv -D SYNTHESIS ../rtl/core/match_engine_pipeline.sv
read_verilog -sv -D SYNTHESIS ../rtl/cam_noisy.sv
read_verilog -sv -D SYNTHESIS ../rtl/cam_top.sv

# Restore verilog defaults
verilog_defaults -pop

# Flattened Xilinx synthesis (includes proc, opt, fsm, memory, etc.)
synth_xilinx -family xc7 -top cam_top -flatten

# Ensure build directory exists for output files
exec -- mkdir -p build

# Write flattened Verilog netlist
write_verilog -attr2comment build/cam_top_synth.v

# Resource statistics (JSON to file via tee, not mixed into logs)
tee -q -o build/cam_top_flat_resources.json stat -tech xilinx -json

# Final checks
check -noinit