SIM_ROOT := $(abspath ../..)
RTL_ROOT := $(abspath $(SIM_ROOT)/../rtl)
include $(SIM_ROOT)/mk/rtl-sources.mk

TOPLEVEL := cam_top
COCOTB_TEST_MODULES := tests.top.test_cam_basic
VERILOG_SOURCES := $(RTL_CAM_TOP)

include $(SIM_ROOT)/mk/cocotb-common.mk