`timescale 1ns / 1ps
`include "cam_params.svh"

module cam_noisy #(
    parameter bit          WRITE_NOISE_EN       = 1'b1,
    parameter int          WRITE_NOISE_RATE_NUM = 1,
    parameter int          WRITE_NOISE_RATE_DEN = 100,
    parameter logic [63:0] WRITE_NOISE_SEED     = 64'hB504_F32D_B504_F32D
) (
    input  logic                              clk,
    input  logic                              rst_n,
    input  logic                              wr_valid,
    output logic                              wr_ready,
    input  logic [(`ROW_BITS)-1:0]            wr_addr,
    input  logic [(`HASH_BITS)-1:0]           write_hash,
    input  logic                              rd_valid_i,
    input  logic [(`ROW_BITS)-1:0]            rd_base_row_i,
    output logic                              rd_valid_o,
    output logic [(`LANES)*(`ROW_BITS)-1:0]   rd_row_ids_o,
    output logic [(`LANES)*(`HASH_BITS)-1:0]  rd_hashes_o,
    output logic [(`LANES)-1:0]               rd_lane_valid_o
);

    // ── Intermediate wires between pipeline stages ──
    logic core_wr_valid;
    logic [(`ROW_BITS)-1:0] core_wr_row;
    logic [(`HASH_BITS)-1:0] core_wr_hash;

    logic core_rd_valid;
    logic [(`LANES)*(`ROW_BITS)-1:0]  core_rd_row_ids;
    logic [(`LANES)*(`HASH_BITS)-1:0] core_rd_hashes;
    logic [(`LANES)-1:0]              core_rd_lane_valid;

    // ── Write noise pipeline ──
    cam_write_noise #(
        .WRITE_NOISE_EN       (WRITE_NOISE_EN),
        .WRITE_NOISE_RATE_NUM (WRITE_NOISE_RATE_NUM),
        .WRITE_NOISE_RATE_DEN (WRITE_NOISE_RATE_DEN),
        .WRITE_NOISE_SEED     (WRITE_NOISE_SEED)
    ) u_write_noise (
        .clk           (clk),
        .rst_n         (rst_n),
        .wr_valid      (wr_valid),
        .wr_ready      (wr_ready),
        .wr_row        (wr_addr),
        .wr_hash       (write_hash),
        .core_wr_valid (core_wr_valid),
        .core_wr_row   (core_wr_row),
        .core_wr_hash  (core_wr_hash)
    );

    // ── Banked synchronous BRAM storage ──
    cam_core_banked u_core_banked (
        .clk             (clk),
        .rst_n           (rst_n),
        .wr_valid        (core_wr_valid),
        .wr_ready        (),
        .wr_row          (core_wr_row),
        .wr_hash         (core_wr_hash),
        .rd_valid_i      (rd_valid_i),
        .rd_base_row_i   (rd_base_row_i),
        .rd_valid_o      (core_rd_valid),
        .rd_row_ids_o    (core_rd_row_ids),
        .rd_hashes_o     (core_rd_hashes),
        .rd_lane_valid_o (core_rd_lane_valid)
    );

    // ── Read noise pipeline ──
    cam_read_noise u_read_noise (
        .clk             (clk),
        .rst_n           (rst_n),
        .valid_i         (core_rd_valid),
        .row_ids_i       (core_rd_row_ids),
        .hashes_i        (core_rd_hashes),
        .lane_valid_i    (core_rd_lane_valid),
        .valid_o         (rd_valid_o),
        .row_ids_o       (rd_row_ids_o),
        .hashes_noisy_o  (rd_hashes_o),
        .lane_valid_o    (rd_lane_valid_o)
    );

endmodule