`timescale 1ns / 1ps

module random128 (
    input  logic         clk,
    input  logic         rst_n,
    input  logic         enable,
    input  logic [127:0] seed,
    output logic [127:0] out
);

    // xorshift128:
    // state = {x, y, z, w}
    //
    // t = x ^ (x << 11)
    // x = y
    // y = z
    // z = w
    // w = w ^ (w >> 19) ^ t ^ (t >> 8)
    //
    // 注意：seed 不能为全 0，否则会永久输出 0。
    function automatic logic [127:0] xorshift128(input logic [127:0] state);
        logic [31:0] x;
        logic [31:0] y;
        logic [31:0] z;
        logic [31:0] w;
        logic [31:0] t;
        logic [31:0] next_x;
        logic [31:0] next_y;
        logic [31:0] next_z;
        logic [31:0] next_w;

        begin
            x = state[127:96];
            y = state[95:64];
            z = state[63:32];
            w = state[31:0];

            t = x ^ (x << 11);

            next_x = y;
            next_y = z;
            next_z = w;
            next_w = w ^ (w >> 19) ^ t ^ (t >> 8);

            return {next_x, next_y, next_z, next_w};
        end
    endfunction

    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            out <= seed;
        end else if (enable) begin
            out <= xorshift128(out);
        end
    end

endmodule