# synth_cam_top_hier.ys — Hierarchy-preserving CAM top resource reference flow
# Run from hw/syn: yosys -s synth_cam_top_hier.ys

# Set include directories before reading RTL
verilog_defaults -push
verilog_defaults -add -I../rtl
verilog_defaults -add -I../rtl/core
verilog_defaults -add -I../rtl/noise
verilog_defaults -add -I../rtl/random

# Read RTL sources in canonical order
read_verilog -sv -D SYNTHESIS ../rtl/random/random128.sv
read_verilog -sv -D SYNTHESIS ../rtl/noise/noise_mask_grouped.sv
read_verilog -sv -D SYNTHESIS ../rtl/noise/cam_write_noise.sv
read_verilog -sv -D SYNTHESIS ../rtl/noise/cam_read_noise.sv
read_verilog -sv -D SYNTHESIS ../rtl/core/cam_core_banked.sv
read_verilog -sv -D SYNTHESIS ../rtl/core/popcount_pipeline.sv
read_verilog -sv -D SYNTHESIS ../rtl/core/candidate_fifo.sv
read_verilog -sv -D SYNTHESIS ../rtl/core/topk_tracker.sv
read_verilog -sv -D SYNTHESIS ../rtl/core/result_serializer.sv
read_verilog -sv -D SYNTHESIS ../rtl/core/match_engine_pipeline.sv
read_verilog -sv -D SYNTHESIS ../rtl/cam_noisy.sv
read_verilog -sv -D SYNTHESIS ../rtl/cam_top.sv

# Restore verilog defaults
verilog_defaults -pop

# Hierarchy check and elaboration
hierarchy -top cam_top -check

# Process and optimize
proc
opt
memory -nomap

# Ensure build directory exists for output files
exec -- mkdir -p build

# Resource statistics (JSON to file via tee, not mixed into logs)
tee -q -o build/cam_top_hier_resources.json stat -tech xilinx -json

# Final checks
check -noinit