`timescale 1ns / 1ps
`include "cam_params.svh"

// Design constraints:
//   HASH_BITS % NOISE_GEN_BITS == 0
//   NOISE_GEN_BITS * NOISE_SAMPLE_BITS == 64
//   0 <= NOISE_RATE_NUM <= NOISE_RATE_DEN
//   NOISE_RATE_DEN > 0
//   NOISE_SEED != 64'd0

module cam_noisy #(
    parameter bit           NOISE_EN          = 1'b1,
    parameter int           NOISE_RATE_NUM    = 1,
    parameter int           NOISE_RATE_DEN    = 100,
    parameter int           NOISE_GEN_BITS    = 8,
    parameter int           NOISE_SAMPLE_BITS = 8,
    parameter logic [63:0]  NOISE_SEED        = 64'hB504_F32D_B504_F32D
) (
    input  logic                                clk,
    input  logic                                rst_n,

    // Write interface (handshake)
    input  logic                                wr_valid,
    output logic                                wr_ready,
    input  logic [(`ROW_BITS)-1:0]              wr_addr,
    input  logic [(`HASH_BITS)-1:0]             write_hash,

    // Read interface (passthrough to cam_core, combinational read)
    input  logic [(`LANES)*(`ROW_BITS)-1:0]     rd_addr_lanes_flat,
    output logic [(`LANES)*(`HASH_BITS)-1:0]    rd_hash_lanes_flat
);

    // ── Elaboration-time parameter checks ──
    initial begin
        if (`HASH_BITS % NOISE_GEN_BITS != 0)
            $fatal(1, "HASH_BITS (%0d) must be divisible by NOISE_GEN_BITS (%0d)", `HASH_BITS, NOISE_GEN_BITS);
        if (NOISE_GEN_BITS * NOISE_SAMPLE_BITS != 64)
            $fatal(1, "NOISE_GEN_BITS*NOISE_SAMPLE_BITS must equal 64, got %0d", NOISE_GEN_BITS * NOISE_SAMPLE_BITS);
        if (NOISE_RATE_DEN <= 0)
            $fatal(1, "NOISE_RATE_DEN must be > 0, got %0d", NOISE_RATE_DEN);
        if (NOISE_RATE_NUM < 0 || NOISE_RATE_NUM > NOISE_RATE_DEN)
            $fatal(1, "NOISE_RATE_NUM (%0d) must be in [0, NOISE_RATE_DEN=%0d]", NOISE_RATE_NUM, NOISE_RATE_DEN);
        if (NOISE_SEED == 64'd0)
            $fatal(1, "NOISE_SEED must be nonzero — xorshift64 with zero seed never advances");
    end

    // ── FSM states ──
    typedef enum logic [1:0] {
        S_IDLE,
        S_GEN_MASK,
        S_COMMIT
    } state_t;

    state_t curr_state, next_state;

    // ── Latch registers ──
    logic [(`ROW_BITS)-1:0]  addr_q;
    logic [(`HASH_BITS)-1:0] write_hash_q;

    // ── Noise generation ──
    logic [63:0] prng_state;
    logic [(`HASH_BITS)-1:0] flip_mask;
    localparam int MASK_GROUPS = `HASH_BITS / NOISE_GEN_BITS;
    logic [($clog2(`HASH_BITS/NOISE_GEN_BITS+1))-1:0] mask_group_idx;  // 0..HASH_BITS/NOISE_GEN_BITS-1

    // ── Precomputed threshold ──
    localparam int SAMPLE_RANGE = 1 << NOISE_SAMPLE_BITS;
    localparam int THRESHOLD    = (NOISE_RATE_NUM * SAMPLE_RANGE) / NOISE_RATE_DEN;

    // ── xorshift64 PRNG function ──
    function automatic logic [63:0] xorshift64(input logic [63:0] x);
        logic [63:0] s;
        s = x;
        s ^= s << 13;
        s ^= s >> 7;
        s ^= s << 17;
        return s;
    endfunction

    // ── Noisy hash for cam_core write ──
    logic [(`HASH_BITS)-1:0] noisy_hash;
    assign noisy_hash = write_hash_q ^ flip_mask;

    // ── wr_ready: only in IDLE ──
    assign wr_ready = (curr_state == S_IDLE);

    // ── FSM block 1: state register ──
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            curr_state <= S_IDLE;
        end else begin
            curr_state <= next_state;
        end
    end

    // ── FSM block 2: next-state logic ──
    always_comb begin
        next_state = curr_state;
        case (curr_state)
            S_IDLE: begin
                if (wr_valid && wr_ready) begin
                    if (NOISE_EN && (NOISE_RATE_NUM > 0))
                        next_state = S_GEN_MASK;
                    else
                        next_state = S_COMMIT;
                end
            end

            S_GEN_MASK: begin
                if (int'(mask_group_idx) == (MASK_GROUPS - 1))
                    next_state = S_COMMIT;
            end

            S_COMMIT: begin
                next_state = S_IDLE;
            end

            default: next_state = S_IDLE;
        endcase
    end

    // ── FSM block 3: state actions / datapath registers ──
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            addr_q         <= '0;
            write_hash_q   <= '0;
            flip_mask      <= '0;
            prng_state     <= NOISE_SEED;
            mask_group_idx <= '0;
        end else begin

            case (curr_state)
                S_IDLE: begin
                    flip_mask      <= '0;
                    mask_group_idx <= '0;
                    if (wr_valid && wr_ready) begin
                        addr_q       <= wr_addr;
                        write_hash_q <= write_hash;
                    end
                end

                S_GEN_MASK: begin
                    // Advance PRNG — sample from NEW state to match ref_model
                    logic [63:0] prng_next;
                    prng_next = xorshift64(prng_state);
                    prng_state <= prng_next;

                    // Generate NOISE_GEN_BITS flip decisions from 64-bit PRNG output
                    for (int b = 0; b < NOISE_GEN_BITS; b++) begin
                        logic [NOISE_SAMPLE_BITS-1:0] sample;
                        sample = prng_next[b * NOISE_SAMPLE_BITS +: NOISE_SAMPLE_BITS];
                        if (int'(sample) < THRESHOLD) begin
                            flip_mask[mask_group_idx * NOISE_GEN_BITS + b] <= 1'b1;
                        end
                    end

                    mask_group_idx <= mask_group_idx + 1;
                end

                S_COMMIT: begin
                    // Write noisy hash to cam_core (one cycle)
                    // cam_core.wr_en is asserted here via comb assign below
                end

                default: ; // No-op
            endcase
        end
    end

    // ── cam_core instance ──
    logic        core_wr_en;
    logic [(`ROW_BITS)-1:0]  core_wr_row;
    logic [(`HASH_BITS)-1:0] core_wr_hash;

    assign core_wr_en   = (curr_state == S_COMMIT);
    assign core_wr_row  = addr_q;
    assign core_wr_hash = noisy_hash;

    cam_core u_core (
        .clk                (clk),
        .rst_n              (rst_n),
        .wr_en              (core_wr_en),
        .wr_row             (core_wr_row),
        .wr_hash            (core_wr_hash),
        .rd_addr_lanes_flat (rd_addr_lanes_flat),
        .rd_hash_lanes_flat (rd_hash_lanes_flat)
    );

endmodule