6 Commits

Author	SHA1	Message	Date
SikongJueluo	d6e1b9d8ba	refactor(cam): rename read-noise path to read-pass-through and reorganize test module structure ... - Rename `read_noise` scenarios and noise_mode to `read_pass_through` across run_cam_correctness.py, test_run_cam_correctness.py, and Makefiles - Update RTL comment in match_engine_pipeline.sv to reflect pass-through behavior - Move unit-level cocotb tests from `tests.test_*` flat namespace to `tests.modules.*` and `tests.top.*` subdirectory layout, matching actual Makefile paths (hw/sim/tests/modules/..., hw/sim/tests/top/...) - Remove redundant dual-noise subtarget from read_noise/Makefile - Update help text and docs to reflect read-path pass-through semantics - Add .codegraph to .gitignore	2026-05-27 16:34:34 +08:00
SikongJueluo	29f4cc91f6	fix(pipeline): add S_WAIT_READ_RESP state to fix read-noise PRNG timing ... - Emit rd_valid_o for exactly one combinational cycle before waiting for read response, ensuring the read-noise PRNG advances once per batch issue - Fix query handshake: wait for query_ready before asserting query_valid to avoid valid&&ready handshake drops on clock edges - Add dynamic timeout estimation in test utilities based on DUT parameters - Update test-top Makefile to run all noise configurations by default - Remove uv run prefix from cocotb-config Makefile invocation	2026-05-22 19:04:50 +08:00
SikongJueluo	e4cbb5e30d	feat(hw/rtl): implement full Top-K CAM search pipeline with serial result output ... - add TOPK_K, FIFO_DEPTH, RESULT_SERIAL parameters to cam_params - add candidate_fifo: synchronous ready/valid FIFO for (row, score) candidates - add topk_tracker: tracks top-K candidates with clear/ready handshake - add result_serializer: serializes packed Top-K array into rank-ordered stream - refactor match_engine_pipeline from 4-state to 8-state Top-K pipeline - extend cam_top with serial Top-K interface (result_rank/row/score/last) - add backward-compatible top1_index/top1_score aliases from rank-0 beat - add comprehensive tests for all new modules	2026-05-19 22:43:21 +08:00
SikongJueluo	8bcad1f23f	refactor(core/cam_core_banked): extract per-bank modules for improved timing isolation ... - Extract cam_bank as a parameterized submodule with independent read/write ports - Replace flat 2D memory array with generate loop of bank instances - Derive bank selection from address bit slicing instead of modulo arithmetic - Align rd_base_row_i check with new bank addressing scheme - Add test verifying bank address isolation across multiple banks	2026-05-19 16:17:08 +08:00
SikongJueluo	706d148a0b	feat(hw): add CAM top-level synthesis infrastructure and fix RTL synthesis compatibility ... - Add hw/syn/Makefile with hier/flat/full synth targets and artifact mirroring - Add synth_cam_top_hier.ys for hierarchy-preserving resource estimation on Xilinx 7-series - Add synth_cam_top_flat.ys for flattened Xilinx 7-series synthesis - Add cam-synth just target for convenient invocation - Guard runtime assertions (NUM_ROWS/LANES checks, noise seed checks, NOISE_BITS checks) behind SYNTHESIS guard in cam_core_banked, cam_read_noise, cam_write_noise, and noise_mask_grouped - Fix shadowed 'return' variable in random128 xorshift128 function	2026-05-18 15:40:04 +08:00
SikongJueluo	0fbcd915bd	refactor: reorganize RTL files into core/noise subdirectories ... - Move CAM core modules (cam_core_banked, match_engine_pipeline, popcount_pipeline) to hw/rtl/core/ - Move noise modules (cam_read_noise, cam_write_noise, noise_mask_grouped) to hw/rtl/noise/ - Update Makefile include paths and VERILOG_SOURCES to reflect new layout - Update docs/experiments.md file path references - Add sim/results.xml to .gitignore - Bump devenv.lock dependencies	2026-05-14 20:59:46 +08:00