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feat(hw): add XNOR-popcount CAM design with cocotb verification
Implement a multi-lane Content Addressable Memory (CAM) that scores rows by XNOR popcount against a query hash and returns the top-1 match. RTL modules: - popcount: parallel group-based population count - argmax_update: iterative best-match tracking with tie-break - cam_core: parameterized scanning engine (NUM_ROWS/HASH_BITS/LANES) with optional SIM_NOISE and SIM_DEBUG ifdef guards - cam_top: thin wrapper exposing cam_core ports Verification: - Python reference model (ref_model.py) for score-level golden comparison - cocotb testbench (test_cam_basic.py) covering write/query/reset and external noise mask scenarios with score debug verification - Noise sweep script (sweep_noise.py) measuring top-1 stability under configurable bit-flip rates - Verilator-oriented Makefile with parameterizable compile options
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214
hw/rtl/cam_core.sv
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214
hw/rtl/cam_core.sv
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`timescale 1ns / 1ps
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module cam_core #(
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parameter int NUM_ROWS = 512,
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parameter int HASH_BITS = 512,
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parameter int LANES = 16,
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parameter int ROW_BITS = $clog2(NUM_ROWS),
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parameter int SCORE_BITS = $clog2(HASH_BITS + 1)
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) (
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input logic clk,
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input logic rst_n,
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// Static load interface. In the first prototype, writes are expected
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// before online queries begin.
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input logic [ ROW_BITS-1:0] wr_row,
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input logic [HASH_BITS-1:0] wr_hash,
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input logic wr_en,
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// Single-request blocking query interface.
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input logic query_valid,
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output logic query_ready,
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input logic [HASH_BITS-1:0] query_hash,
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output logic result_valid,
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input logic result_ready,
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output logic [ ROW_BITS-1:0] top1_index,
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output logic [SCORE_BITS-1:0] top1_score,
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`ifdef SIM_NOISE
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// Flattened for easier cocotb/Verilator handling:
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// lane k mask = noise_mask_lanes_flat[k*HASH_BITS +: HASH_BITS]
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input logic [LANES*HASH_BITS-1:0] noise_mask_lanes_flat,
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`endif
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`ifdef SIM_DEBUG
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// Flattened for easier cocotb/Verilator handling:
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// score[row] = score_debug_flat[row*SCORE_BITS +: SCORE_BITS]
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output logic [NUM_ROWS*SCORE_BITS-1:0] score_debug_flat,
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`endif
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output logic busy
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);
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localparam int NUM_BATCHES = (NUM_ROWS + LANES - 1) / LANES;
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typedef enum logic [1:0] {
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S_IDLE,
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S_SCAN,
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S_DONE
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} state_t;
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state_t state_q, state_d;
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logic [HASH_BITS-1:0] cam_mem[NUM_ROWS];
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logic [HASH_BITS-1: 0] query_q;
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logic [ROW_BITS-1 : 0] base_row_q;
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logic [ROW_BITS-1 : 0] base_row_d;
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logic [ROW_BITS-1:0] best_index_q, best_index_d;
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logic [SCORE_BITS-1:0] best_score_q, best_score_d;
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logic [ ROW_BITS-1:0] lane_best_index;
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logic [SCORE_BITS-1:0] lane_best_score;
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logic [ ROW_BITS-1:0] lane_best_index_next[LANES+1];
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logic [SCORE_BITS-1:0] lane_best_score_next[LANES+1];
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logic [SCORE_BITS-1:0] lane_score [ LANES];
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logic [ ROW_BITS-1:0] lane_row [ LANES];
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logic lane_valid [ LANES];
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assign query_ready = (state_q == S_IDLE);
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assign result_valid = (state_q == S_DONE);
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assign top1_index = best_index_q;
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assign top1_score = best_score_q;
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assign busy = (state_q == S_SCAN);
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// Memory write path.
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always_ff @(posedge clk) begin
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if (wr_en) begin
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cam_mem[wr_row] <= wr_hash;
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end
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end
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`ifdef SIM_DEBUG
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// Clear by default. Individual rows are overwritten during scan.
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initial begin
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score_debug_flat = '0;
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end
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`endif
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genvar lane;
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generate
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for (lane = 0; lane < LANES; lane++) begin : gen_lanes
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logic [HASH_BITS-1:0] row_hash;
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logic [HASH_BITS-1:0] effective_hash;
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logic [HASH_BITS-1:0] match_bits;
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assign lane_row[lane] = base_row_q + lane[ROW_BITS-1:0];
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assign lane_valid[lane] = (lane_row[lane] < NUM_ROWS[ROW_BITS-1:0]);
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// This read is modeled behaviorally. Later this can be replaced
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// by banked BRAM/URAM without changing the compare path.
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assign row_hash = lane_valid[lane] ? cam_mem[lane_row[lane]] : '0;
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`ifdef SIM_NOISE
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logic [HASH_BITS-1:0] lane_noise_mask;
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assign lane_noise_mask = noise_mask_lanes_flat[lane*HASH_BITS+:HASH_BITS];
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assign effective_hash = row_hash ^ lane_noise_mask;
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`else
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assign effective_hash = row_hash;
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`endif
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assign match_bits = ~(query_q ^ effective_hash);
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popcount #(
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.WIDTH(HASH_BITS),
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.GROUP(8),
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.OUT_WIDTH(SCORE_BITS)
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) u_popcount (
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.bits_i (match_bits),
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.count_o(lane_score[lane])
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);
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argmax_update #(
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.ROW_BITS (ROW_BITS),
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.SCORE_BITS(SCORE_BITS)
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) u_argmax_lane (
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.best_index_i(lane_best_index_next[lane]),
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.best_score_i(lane_best_score_next[lane]),
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.cand_index_i(lane_row[lane]),
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.cand_score_i(lane_valid[lane] ? lane_score[lane] : '0),
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.best_index_o(lane_best_index_next[lane+1]),
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.best_score_o(lane_best_score_next[lane+1])
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);
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end
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endgenerate
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assign lane_best_index_next[0] = best_index_q;
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assign lane_best_score_next[0] = best_score_q;
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assign lane_best_index = lane_best_index_next[LANES];
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assign lane_best_score = lane_best_score_next[LANES];
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always_comb begin
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state_d = state_q;
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base_row_d = base_row_q;
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best_index_d = best_index_q;
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best_score_d = best_score_q;
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unique case (state_q)
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S_IDLE: begin
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if (query_valid) begin
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state_d = S_SCAN;
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base_row_d = '0;
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best_index_d = {ROW_BITS{1'b1}};
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best_score_d = '0;
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end
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end
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S_SCAN: begin
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best_index_d = lane_best_index;
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best_score_d = lane_best_score;
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if (base_row_q + LANES >= NUM_ROWS) begin
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state_d = S_DONE;
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end else begin
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base_row_d = base_row_q + LANES[ROW_BITS-1:0];
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end
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end
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S_DONE: begin
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if (result_ready) begin
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state_d = S_IDLE;
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end
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end
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default: begin
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state_d = S_IDLE;
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end
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endcase
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end
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state_q <= S_IDLE;
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query_q <= '0;
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base_row_q <= '0;
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best_index_q <= '0;
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best_score_q <= '0;
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end else begin
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state_q <= state_d;
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base_row_q <= base_row_d;
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best_index_q <= best_index_d;
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best_score_q <= best_score_d;
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if ((state_q == S_IDLE) && query_valid) begin
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query_q <= query_hash;
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end
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`ifdef SIM_DEBUG
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if (state_q == S_IDLE && query_valid) begin
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score_debug_flat <= '0;
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end else if (state_q == S_SCAN) begin
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for (int l = 0; l < LANES; l++) begin
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if (lane_valid[l]) begin
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score_debug_flat[lane_row[l]*SCORE_BITS+:SCORE_BITS] <= lane_score[l];
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end
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end
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end
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`endif
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end
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end
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endmodule
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